As I noted in my post of my transcription of this magazine article, if you're a fan of Motorola's 6809 Advanced 8-bit CPU, you may be aware of Hitachi's 6809-compatible 6309 CPU. You may have heard of the article that "revealed" the 6309's extensions to the 6809 register model and instruction set.
I am not especially a fan of the 6309, although I am something of a fan of the 6809. But there are many fans of the 6809 who are also fans of the 6309, and I've heard enough of them ask for a translation of this article, and I happen to be spinning my wheels in my more important goals at the moment, so I've decided to take a crack at it.
Today (Saturday, May 7, 2022), I just finished typing in the background portion of the article in Japanese, and that is probably the more interesting part, anyway. Over the next several months or longer, when I'm not too tired from the mail route, I'll either be typing more of the article in on the transcription post, or I'll be translating more of it here. Right now, I only have the first pass on the headline and the first paragraph in English.
I don't really want to work with the output of
Google Translate
here, because I find it distracting. (But people will ask for it, and I
guess it's not necessary to make everyone go to Google themselves, so I'll
paste it below for while I work, and to laugh at when I'm done.)
If the publishers of Oh! FM or the authors of the article take
exception to me putting this up without permission, yes, I'll take it back
down. It's so long water under the bridge that it's hard to imagine anyone
thinking the information will do anyone damage now, but you never know.
The beginning of the translation, just text for now, with a tiny bit of
crude markup:
The background sections are now (around May 21st) done, and I'm leaving the Japanese mixed in here for reference.
[JMR202206082344:
And now (June 8th) the rest of the technical details section has been typed up and posted in the transcription post linked above. I'll begin translating it here real soon now, beginning at
************
拡張レジスタ
Extension registers
But I'll note again that the technical information in the article should be considered to be for historical interest only. The technical reference by Alan DeKok and Chet Simpson at
http://www.sandelman.ottawa.on.ca/People/Alan_DeKok/interests/6309.techref.html
is more complete and more accurate.
For further reference, the reportage by Hirotsugu Kakugawa which made the meat of the technical information widely available and led to the reference above can be found on comp.sys.m6809, archived by Google at https://groups.google.com/g/comp.sys.m6809/c/xxCoMu_gyA4/m/-mhmKurDc90J .
]
[JMR202206262027:
Translation of the entire article is now complete.
There is no purpose in this other than historicity, so I will not be posting an English-only version of the article. Also, I cannot grant permission to copy.
]
It should be remembered that this was written almost forty years ago, and much of what the (apparently pseudonymous) authors say is old news and dated marketing hype.
Since I don't own the original copyrights, I cannot extend permission to copy
or publish in any way. Partly for that reason, I do not plan to publish an
English-only version. Go ahead and wade through the mix. If you feel inclined,
try reading the Japanese.
The translation, mixed in with the transcription:
[Original copyright 1988 Oh!FM -- 元発行社 Oh!FM 1988]
[Translation
copyright 2022 Joel Matthew Rees -- 翻訳文発行者 Joel Matthew Rees 2022]
[Oh!FM 1988-4: p.72]
=================================================
１６ビット乗除算／レジスタ間演算／ブロック転送が可能
16-bit
Multiplication & Division / Register-register Math / Block Transfers
超８ビット級ＭＰＵ
8-bit
Super MPU
63C09の拡張機能をさぐる
Finding Extensions to the 6809 in
the 63C09
63C09解析委員会 UNO
63C09 Survey Committee (Kaiseki
Iinkai) UNO
6809のマイナーチェンジ版に、63C09というLSIがあります。ハードに強い一部のユーザの間では、その高速性を買われ、本体の改造に使われたりしてきました。ところが、最近この63C09に各種の拡張機能が隠されていたことがわかりました。ここでは、それらの機能を発見し、探索してきた「63C09解析委員会」の方にその概要を報告していただきます。
The
63C09 is known as a minor upgrade to the 6809. Some users who have confidence
with hardware have bought it for the higher speed rating, to speed up their
computers. Recently, various hidden functional enhancements have been
discovered in the 63C09. Here, we will have someone from the 63C09 Survey
Committee (Kaiseki Iinkai) that found and explored these extensions outline
what they have brought to light.
なお、本体の改造、ことにＣＰＵの差し換えは、メーカーの修理は保証されず、他の周辺ＬＳＩ、周辺機器も交換しなければならない場合もありえ、おまけに63C09だと従来のソフトの一部（あるいは多数）が動作しなくなる危険性がありますので、「私は自作したプログラムしか使わない！」という、よほど腕に自信のある方以外にはお勧めしかねます。
Now,
we need to point out the dangers. When you start adding your own custom
modifications to your computer, in particular when you swap out the CPU, the
manufacturer is not guaranteed to fix your mistakes for you. It is possible
that you will be required to change out other LSI parts and peripherals as
well. And with the 63C09 you may end up losing the ability to run some -- or
even most -- of the software you've been relying on, to boot. For these
reasons, we cannot recommend these modifications, except to those who have a
very high level of confidence in their own skills, to the point that they are
willing to forego the use of any software they don't themselves write.
******************
6809の高速版 63C09
The 63C09 as a High-Speed 6809
パソコンの楽しみ方には色々ありますが、その筋の兵[つわもの]だけに許された遊びとして、ハードの改造があります。その昔からいろいろな改造が行なわれてきましたが、中でもＣＰＵの高速化は、処理能力の向上が著しいことと、比較的簡単に行えることから、市販ソフトに頓着しないプログラム自作派の間では広く試みられてきました。古くは
FM-8 に積まれた 68A09 (1.2 MHz) を 68B09 (2 MHz) に変えて、
FM-7並の処理速度を与えたこと、最近では FM-11
を中心にＣＰＵをクロックアップして 2.5~4 MHz
で動かすことが、その代表的なところです。
There are many ways to have fun
with a personal computer, but one game that is only allowed the adept is
customizing your hardware. There have been a number of traditional
customizations, accelerating your CPU stands among them out for improving the
functional speed of your computer. Since it is relatively easy to do, it is
popular among DIY-ers who do not get overly concerned about commercial
software. In the past, one might trade the 1.2 MHz 68A09 in an FM-8 for a 2
MHz 68B09, to give it speed comparable to the FM-7. More recently,
overclocking the processor at speeds of 2.5~4 MHz has become common,
especially with the FM-11.
「えっ、 2.5~4MHz だって、そんなに速い
6809ってあったっけ」と思われる方もおられるでしょうが、実は存在するのです。秋葉原や日本橋のチップ屋さんで売っている日立の
63C09 というＭＰＵがそれで、 3 MHz で動作する、
6809のC−MOS版です。ノーマルに従うなら従来の 68B09 (2 MHz) の
1.5倍の処理能力になり、選別して規格外の 4 MHz
で動くものを使えば２倍の処理能力となります。
Many people will be
thinking, "Huh? 2.5 to 4 MHz? Are there 6809s that fast?" Yes. There are.
Hitachi's 63C09, available at chip shops in Akihabara and Nihonbashi, is a
C-MOS 6809 that operates at 3 MHz. Standard parts are rated at 1.5 times the
speed of the (2 MHz) 68B09, and if you use a specially selected part, you can
run it out of spec at 4 MHz, to give double the functional speed.
この 63C09
を使って高速化を行うわけで、基本的にはＣＰＵとクロックを差し換えるだけの簡単なものですが、それだけでは済まないこともあります。
FM-8, 7, 77D1/D2/L4, 77AV, 11
のようにＣＰＵがソケットに差さっている機種では単純に差し換えるだけですが、
FM-NEW7, 77AV20/40/20EX/40EX
のように基板に直接ハンダづけされている機種ではかなりの腕がないとＣＰＵが引っこ抜けません。また、クロックアップした場合周辺ＬＳＩや周辺機器が追いつかないこともあり、その場合はそれらも交換しなければなりませんが、ＡＶ系のようにカスタムＬＳＩが多用されている場合は難しいでしょう。
7/AV系のサブシステムのように微妙なタイミングで動いているものでは、クロックアップはかなり困難で、しかも、クロックアップしたが最後、プロテクトやその他の処理に内蔵タイマやソフトウェア的なタイミングを使った市販アップリケーションソフトの多くは全て使いものにならなくなってしまいます。
Using
the 63C09 to accelerate your computer may be basically a matter of replacing
the CPU and clock, but it's not always that simple. With models which have
socketed CPUs, such as FM-8, 7, 77D1/D2/L4, 77AV, and 11, it's just a matter
of replacing the chips. But with models that have the parts soldered directly
to the board, such as the FM-NEW7 and 77AV20/40/20EX/40EX, it requires a fair
degree of skill to get the CPU out. Also, when increasing the clock speed, the
support LSI ICs and external peripheral devices may not be able to keep up. In
that case, you must trade those out as well. With models which, like the AV
[audio/video => multimedia] models, use many custom LSI parts, this can be
exceedingly difficult [meaning, impossible]. With models which push
specification limits, such as the 7/AV series, raising the clock rate can
leave you unable to access most commercial application software which uses
internal timers or software timing for processes such as [copy]
protection.
さて、これら様々な困難を伴った高速化ですが、そのもたらす結果は苦労を補って余りあるものです。
So,
accelerating your computer comes with a wide range of problems, but the
results well make up for the effort.
ちなみに FM-11
の場合を例にとると、ＣＰＵの差し換えだけだと 2.5~3 MHz
ぐらいが限界のようで、それ以上を望むと一部周辺ＬＳＩの差し換え等が必要なようです。
11ではサブシステムの高速化も可能で、手を加えれば 4 MHz までいけます。とくに、
4 MHz化された FM-11
のサブシステムの表示速度は目を見張るものがあり、漢字の表示速度が漢字ＶＲＡＭをもった
FM16β と大差ない速さになります。
As an aside, taking the FM-11 as an
example, just swapping out the CPU has a limit of 2.5 to 3 MHz gain. Getting
more out of it will require changing out some of the support LSI and
peripherals, etc. With the 11, subsystems can also be accelerated so that,
with a little effort, 4 MHz speeds can be obtained. Accelerated to 4 MHz, the
FM-11 subsystems display speed is astounding, with Kanji display speed not
very different from the Kanji VRAM-equipped FM16β.
*************
拡張機能の発見
Discovering
the Functional Extensions
というわけで、私の周りの歴戦の勇士たちは次々と
FM-11 に高速化改善を行ったのですが、そこに１つ、奇妙な問題が発生しました。
Which
is why the brave wizards around me, one after another, accelerated their
FM-11s. But a rather curious problem occurred.
コマスのワープロＷＰＶ３が動かなくなってしまったのです。最初は、前述したソフト的なタイミングの問題か何かだと思われたのですが、驚いたことに、クロックを
2 MHz に落としても動きません。
Comas's word processor, WPV3, would not
work. At first, we suspected the sort of software timing issues I mentioned
above, but, to our surprise, when we brought the clock back down to 2 MHz, it
still didn't run.
そこで、友人の
Gigo氏を中心に原因探究が始まったのですが、ほどなく 6809
の未定義命令で引っかかっていることがわかりました。未定義命令とは、メーカが発表しているマニュアルで定義されていない命令のことで、建前上はそのような命令を使ってもなんの動作もしないことになっているのですが、実は隠し命令になっていることもままあります。一昔のパソコン雑誌には、よく各社製ＣＰＵの隠し命令の解析記事が載っていたりしました。このよう
Investigation
began at this point, and, with a friend I'll call Mr. Gigo taking a lead role,
we quickly found that it was getting stuck at unimplemented 6809 instructions.
Unimplemented instructions are instructions that are not defined in the
manufacturer's manuals, and fundamentally should not be expected to do any
[particular] thing, but it's not unusual that they are in fact hidden
instructions. A short time ago, you would find articles detailing hidden
instructions for each manufacturer's CPUs in Pasokon [nascent personal
computer] magazines. Such
--------
７２ Oh!FM 1988-4
警告 ＣＰＵを 63C09
に交換した場合、かなりの市販アプリケーション（とくにゲーム）が動作しなくなります。
p.
72 Oh! FM 1988-4 Warning: Exchanging the CPU for the 63C09 will result
in many commercial applications (especially games) failing to run.
--------
[Oh!FM
1988-4: p.73]
な隠し命令は、 6809
にもそう大したものではありませんでしたがありました。さて、未定義命令の扱いが
63C09 と 6809 とでは異なるということは、隠し命令も異なる可能性があるわけです。
63C09 の出荷開始時期 (1985年秋)
を考えても、何か機能が追加されても当然なくらいで、「もしかしたら」の期待がわきました。
hidden
instructions on the 6809 are not very special, but do exist. Differences in
the effects of unimplemented instructions probably implies differences in
hidden instructions. Considering the timing of the introduction of the 63C09
(Fall 1985), it might even be expected that some additional functionality was
included. We began to get excited about the what-ifs.
引っかかっているコードの１つに「$1F,
$62」というものがありました。命令自体は TFR
（レジスタ間のデータ転送命令）でおなじみのものですが、未定義レジスタから Y
レジスタへ転送するように指示されています。 6809 の場合は未定義なので Y
レジスタに $FFFF が返りますが、63C09 の場合は Y
レジスタにはめちゃくちゃな[値]が入ります。試みに、 Y
レジスタから未定義レジスタ番号にデータ転送してから未定義レジスタ番号から Y
レジスタへ戻してやると、元のデータがちゃんと残っていました……。つまり、 63C09
の未定義レジスタ番号は、番号が余って未定義となっていたのではなく、実在するレジスタを指す番号だったのです！
One
of the codes it was getting stuck at was $1F, $62. The instruction itself is
the familiar TFR (register-to-register transfer) instruction, but it specifies
copying the value from an unimplemented register to the Y register. On the
6809, it is unspecified, but the value $FFFF is returned to Y. On the 63C09, Y
gets loaded with an absurd value. As a test, when a [known] value was
transferred from Y to the unimplemented register number and then returned from
the unimplemented register number to Y, the value nicely left in Y was the
original value .... In other words, on the 63C09, the unimplemented register
number was not just a leftover number specifying an unimplemented register, it
specified an actually existing register!
その隠しレジスタを発見した
Gigo氏は、狂喜してかたっぱしから友人に電話をかけまくりました。そして、私のところにも夜も丑三つ[うしみつ]時[dead
of the night]過ぎにかかってきました……。話の内容は、「63C09
にはレジスタが余計にある。レジスタがあるからには命令もあるはずだ。みんなで手分けして調べよう」というもので、それから隠し命令を探す日日が始まり、ディスアセンブル表の割り当てのないコードをデバッガでメモリ上に書き、ブレークポイントを設定して
TFR
でレジスタに値をセットして実行させ、レジスタの内容を見るという単調な作業が繰り返されました。その日わかった結果を、パソコン通信を通じて情報交換するうちに、いつとはなしに、
FM-11 で OS-9 をやっている、それもほとんど病気に近いマニアが集まり、「63C09
解析委員会」なる集団が自然発生しました。
Mr. Gigo, who discovered the
hidden register, in his rapture, immediately called all his friends one after
another. It was beyond the dead of night when he called me. The substance of
his call was, "The 63C09 has extra registers. It it has registers, it ought to
have instructions, too. Let's split up the work and see what we can find."
Thus began long days of the monotonous job of hunting hidden instructions by
using a debugger to repeatedly write codes that are unallocated in the
disassembly table into memory, set breakpoints and use TFR to set values in
registers and execute the instructions, and check the register contents. Each
day we would share our results, communicating by personal computer networks,
and, before we knew it, a group of almost ill maniacs who run OS-9 on their
FM-11s had naturally coalesced into the "63C09 Survey Committee".
[The
grammar in the Japanese here is a bit murky. I think he should have said
something like, "... by repeatedly selecting unallocated codes from the
disassembly table and using the debugger to create test routines by (1)
writing them into memory sandwiched between TFR codes which set values in
registers and then extract the values to check them, (2) setting breakpoints,
and (3) executing the test routines". But the language in the article is not
that precise, and I can't find enough clues to justify that much
interpolation. If you've done this, you know what he means. If you haven't,
you'd need a full article, blog post, or video describing the process. It has
been done. Might be fun to do my own, if I had the time.]
マニアの執念は恐ろしいもので、ほどなく
36C09 の拡張機能の大筋が判明しました。概略を述べると、
・３種類のレジスタが増設されており、そのうちの１つはアキュムレータとして、またインデックスレジスタとして使える
・32÷16
ビット除算、 16÷8 ビット除算、 16×16
ビット乗算、レジスタ間演算、ビット操作、ブロック転送などの命令が拡張されている。
・未定義の命令を検出した場合トラップがかかる
・6809
コンパチのモードと、 63C09 本来のモードの２種類の動作モードをもつ
といったところで、今までの
6809
で不便であった部分、弱点であった部分が相当改善されており、またとても８ビットＭＰＵとは思えない強力な機能も含まれています。
Fanatical
obsession can be scary. Before long, we had the general outline of the
extended functionality fleshed out. In brief,
* 3 classes of
registers have been added, one of which can be used either as an accumulator
or as an index register;
* the extended instruction set includes 32-by-16
bit divide, 16 by 8 bit divide, 16 by 16 bit multiply, register-register math,
bit operations, block moves, and such;
* a trap is triggered when
unimplemented instructions are found;
* and there are two operating
modes, a 6809 compatible mode and a 63C09 native mode.
Here we have
many inconveniences or straight-out weaknesses in the 6809 which are rather
improved, and functionality which is hard to think of as existing in an 8-bit
MPU is included.
これらの解析結果はＮＡＮＮＯ−ＮＥＴを皮切りに、いくつかの
BBS
にアップされました。多くのネットワーカーの方から多大な反響を得ましたが、より多くの方に「８ビットを超える８ビットＭＰＵ」
63C09 の全貌[ぜんぼう=entire body]を知っていただくために、 Oh!FM
の誌上お借りしてご報告します。
The results of our analyses have been
uploaded to several BBSses, beginning with NANNO-NET. They have been
well-received among net-walkers [among netizens? in the on-line communtity],
but now we are borrowing magazine space in Oh!FM to make the full nature of
the more-than-8-bit 63C09 8-bit MPU known among a broader audience.
*******************
63C09化の
メリット／デメリット
Considerations
in
Converting to the 63C09
[Merits/demerits =>
Advantages/disadvantages => Considerations]
日立から販売されている
HD63C09 は、モトローラの MC6809
とピンコンパチの８ビットＭＰＵです。ＭＰＵの仕様は 6809
に拡張機能を付け加えた形のもので、
6809の上位コンパチになっています（未定義の命令を除く）。日立から公式発表はされていませんが、
63C09 の拡張機能を活用すると、
6809パソコンの処理能力を大幅に向上させることができます。
Hitachi's 63C09
is a 6809 pin-compatible 8-bit MPU. It is specified as upward compatible with
the 6809 (excepting 6809 unimplemented op-codes) with extended functionality.
The functionality is not publcally acknowledged by Hitachi, but using the
extended functionality of the 63C09 can yield significantly improvements over
the performance of the 6809.
6809パソコンのＭＰＵを 63C09
に差し換えた場合のメリットは処理能力の向上につきます。その要因としては以下の３点が考えられます。
The
merits of replacing the MPU in a 6809-based personal computer are found in the
improved performance. These three factors can be considered:
１ 高速クロック
２ 拡張命令／拡張レジスタ
３ ネイティブモード
1:
Higher-speed clock
2: Instruction/register extensions
3: Native
mode
１は当然のことで、ＭＰＵの動作クロックをあげればソフトの実行速度は上がります。未定義命令トラップやソフトウェアタイマの関係で引っかかる一部を除けば、従来のソフトが高速に動かせます。動作クロックの上昇率はハードにより異なり、場合によってはほとんどあげられないこともあります。
The
merits gained from the first factor are a matter of course -- if you raise the
MPU's processor clock rate, programs runs faster. Except for certain programs
that will have problems related to unimplemented instruction traps, software
timers, and such, existing software runs faster unchanged. How fast the clock
can run depends on the hardware, and there are some cases where the clock can
hardly be raised at all.
２は、新規にソフトを書き起こすか、従来のソフトにパッチを当てたときに効果があります。従来の
6809 だとアセンブラのマクロ機能で表現していた処理の相当が 63C09
の１命令で書けるようになり、マシンサイクルを短縮できます。
Merits due to
the second factor only come into play when writing new software new or
patching existing software. Many operations that would be expressed as macros
in the existing 6809 instruction set are performed by a single instruction on
the 63C09, reducing machine cycle count.
３は、
63C09固有のモードに切り換えて使うと、通常のエミュレーションモードよりも命令の実行サイクルが短くなることにより生じるものです。このモードを使うと、同じ動作クロックでも、通常より実行速度が最大20〜30％上がります（アドレッシングモードにより効果が違う）。ただ、スタックや割り込み関係で動作が異なる点があるので、ネイティブモードを利用するには
F-BASIC なり OS-9 なりのシステムの一部を書き換える必要があります。
Merits
from the third factor are obtained by switching to native mode, in which
instruction execution cycles are reduced over the normal emulation mode. When
using this mode, run speed can increase as much as 20 to 30%, even at the same
operation clock (varies according to addressing mode). However, due to
differences in handling the stack and interrupts, in order to use native mode,
parts of your system (F-BASIC, OS-9, etc.) must be rewritten.
逆にデメリットとしては、まず、
6809
の未定義命令を使ったソフトに限らず、多くの内蔵タイマを使った市販ソフトその他が動作不良を起こしてしまうであろうこと、また、
63C09
の拡張機能を活用するにはそれらを活用するための開発ツールを自作できるくらいのそれなりの腕が必要で、ノービスには難しいことが難点といえるでしょう。
Looking
on the other hand at the demerits, first off, besides the different effects of
unimplemented instructions in the 6809, commercial software which uses
internal timers will tend to function erratically. Also, the skills to produce
tools that take advantage of the 63C09 extensions must be produced oneself,
which will be a point of difficulty for the novice user.
メリットとデメリットを比較すると、現状では自分でプログラム書くだけの人ならその恩恵を受けることができるが、ごく一般のゲームユーザやアプリユーザは決して手を出さないほうがよい、といったところでしょう。
Comparing
the merits and demerits, under the present conditions those who can write
their own programs can receive the benefits of the 63C09, but game and
application users in general should pass this one by.
それでは、
63C09 の拡張機能について以下順番に解説していきます。
With that, we shall
proceed to describe the extended functionality of the 63C09.
**********************
[The essential content of the technical description is already available at
http://www.sandelman.ottawa.on.ca/People/Alan_DeKok/interests/6309.techref.html.I may go ahead and translate what the article has, for completeness. But
the above link will provide more correct information, now. So, if I
do,
I'll be working on the technical sections at lower priority.]
**********************
************
拡張レジスタ
Extension registers
63C09
では 6809 よりレジスタの数が３つ増えています（図１）。そのうち２つは
16ビットのレジスタで、もう１つは８ビットのモードステータスレジスタです。
The
63C09 has three more registers than the 6809 (Table 1). Two of those registers
are 16-bit registers, and one is an 8-bit mode/status register.
Wレジスタ［16ビット］
W
Register (16 bit)
~~~~~~~~~~~~~~~~~~~~
アキュムレータとしても、インデックスレジスタとしても使用できる
16ビットレジスタです。
16 bit register useable as either an accumulator
or an index register.
アキュームレータとして使うときは、 16ビ
When
used as an accumulator,
--------
Oh!FM 1988-4 ７３
Oh! FM
1988-4 p. 73
--------
[Oh!FM 1988-4: p.74]
ットレジスタとしてのほか、２つの８ビットレジスタ（E/Fレジスタ）に分割して使うこともできます。ちょうど、既存の
D/A/Bレジスタがもう１組増えたようなものです。ただし、 AND/OR 等の W/E/F
レジスタでは使えない命令もあります。
in addition to being useable as a
16-bit register, W may be split and used as two 8-bit registers (E/F). This is
just like having an extra D/A/B register, except that there are instructions
such as AND and OR that cannot be used with W/E/F.
また、既存の
Dレジスタと連結して
32ビットレジスタ（Qレジスタ）として使うことができ、乗除算のときに利用します。
It
can also be concatenated with the existing D register and used as a 32-bit
register, useful in division operations.
インデックスレジスタとして使うときは、既存の
X/Yレジスタと同様に利用します。この場合、 6809
でポストバイトに用いられていないビットパターンを使用します。Wレジスタをインデックスレジスタとして使用したときの、アキュムレータオフセットと５ビットオフセット、８ビットのコンスタントオフセットはありません。
W functions similarly to the existing x and Y registers when used as an index.
In this case, it uses a post-byte bit pattern that is not used on the 6809.
However, when using the W register as an index, accumulator, 5-bit, and 8-bit
offsets are not available.
また、特徴な使い方として、ブロック転送でのカウンタレジスタとして使う方法があります。
As
a specialized use, W is used as the counter in block transfer operations.
Vレジスタ［16ビット］
V
Register (16-bit)
~~~~~~~~~~~~~~~~~~~~
Vレジスタを使う命令は、レジスタ間演算命令や
TFR
などに限られています。Vレジスタの特徴は、ＭＰＵをリセットしてもレジスタの値が変化しないことです。このレジスタをＯＳなどで定数等を保持するような目的に便利でしょう。
Instructions
that use the V register are limited to register-register math and TFR, etc.
The special feature of the V register is that its value is not changed, even,
when you reset the MPU. This register could be useful for tracking constants
and such, for example, in operating system code.
MDレジスタ［８ビット］
MD
Register (8-bit)
~~~~~~~~~~~~~~~~~~~~
モード／ステータスビットレジスタの略で、除算実行時のエラー検出や未定義命令トラップの作動チェック、動作モードの設定など、
63C09
になって増えたモードやステータスの表示に用いられます。各ビットの意味は次のとおりです。
Abbreviated
MD for mode/status bit register, this register is for accessing the modes and
status that the 63C09 adds, including testing for divide-time errors and
checking for undefined instruction traps, and for setting the operating mode,
etc.
・ビット７ Ｒ 除算で 0 で割ったときに 1 がセットされる ・ビット６ Ｒ 未定義命令をフェッチしたときに 1 がセットされる ・ビット１ Ｗ FIRQ時のレジスタの退避モード設定ビット 0 -> FIRQ時、 PC と CC のみスタックに退避 1 -> FIRQ時、 すべてのレジスタを退避 ・ビット０ Ｗ 動作モード設定ビット 0 -> エミュレートモード 1 -> ネイティブモード
* bit 7 (R): set to 1 on divide-by-zero
* bit 6 (R): set to 1 on an undefined instruction fetch
* bit 1 (W): bit to set the FIRQ register save mode
0 -> on FIRQ, only save PC and CC
1 -> on FIRQ, save all registers
* bit 0 (W): bit to set the operating mode
0 -> emulation mode
1 -> native mode
なお、リセット時にはすべてのビットは 0 になります。
On reset, all bits
are set to 0.
図１ 63C09レジスタ構成 __________________________________________________ |----------Q----------| |----D----| |----W----| |-A-| |-B-| |-E-| |-F-| アキュムレータ ----------- |----X----| X インデックスレジスタ ----------- |----Y----| Y インデックスレジスタ ----------- |----U----| ユーザスタックポインタ ----------- |----S----| システムスタックポインタ ----------- |---PC----| プログラムカウンタ ----------- |----V----| V(alue) レジスタ ----------- |---DP----| ダイレクトページレジスタ ----------------- |CC-| コンデションコードレジスタ ----------------- |MD-| モード／ステータスレジスタ __________________________________________________
Table 1: 63C09 Registers _________________________________________________ |----------Q----------| |----D----| |----W----| |-A-| |-B-| |-E-| |-F-| Accumulatorx ----------- |----X----| X index register ----------- |----Y----| Y index register ----------- |----U----| User stack pointer ----------- |----S----| System stack pointer ----------- |---PC----| Program counter ----------- |----V----| V(alue) register ----------- |---DP----| Direct page register ----------------- |CC-| Condition code register ----------------- |MD-| Mode/status Register __________________________________________________
*********
動作モード
Operating Modes
63C09には２つの動作モードがあります。１つは
6809 とのコンパチビリティを考えたエミュレートモードで、もう１つは 63C09
の本来の機能を引き出すネイティブモードです。
The 63C09 has two operating
modes. One is the 6809 compatibility emulation mode, and one is the 63C09
native mode that brings out it's own functionality.
と、いうと、「拡張レジスタや拡張命令が使えるのがネイティブモードで、使えないのがエミュレートモードだな」と思われる方もいるでしょうが、それはハズレです。
63C09 では、拡張レジスタと拡張命令をどちらのモードでも使えます。
That
said, some will think, "The mode which makes the extension registers and the
instructions available is the native mode, right?" But that is not correct.
The extension register and instruction set are accessible in either mode.
エミュレートモードとネイティブモードの違いは、インタラプト時のスタックの扱いの違いです。インタラプトがかかったときレジスタの内容はスタックに退避されますが、そのとき従来からのレジスタだけを退避させるのがエミュレートモードで、拡張レジスタの
W レジスタも退避させるのがネイティブモードです。
The difference between
emulation mode and native mode is how the stack is handled at interrupt time.
The register contents are saved on interrupt, but the mode that saves only the
original register set is the emulation mode, and the mode that saves all the
extension registers as well is the native mode.
63C09
をリセットした直後はエミュレートモードに設定されています。このモードでは 6809
のソフトが問題なく動作する代わり、マルチタスクで拡張レジスタを使うときに気をつけなければなりません。たとえば、拡張レジスタの
W レジスタをカウンタに使うブロック転送命令 TFM
を使ったケースを考えます。タスクＡで TFM
命令を使用中に、インタラプトをかけて、タスクＢに移ったとしましょう。そのときにタスクＢで
W レジスタを使用したとしたら、また元のタスクＡに戻ったときに W
レジスタの中身が変更されていますので、誤動作を起こします（もちろんシングルタスクで使用するときや、マルチタスクでも１つのタスクでしか拡張レジスタを使用しないときは問題ありません）。よって、エミュレートモードでは、拡張レジスタを使用するときはいちいちインタラプト禁止して、さらにこのレジスタを一度スタックにセーブしてからでないと、別タスクに切り換えてはなりません。
Immeditiately
after reset, the 63C09 is in emulation mode. In this mode, software for the
6809 executes without problems, but you must be careful when using the
extension registers in multitasking. For example, consider using the block
transfer instruction TFM, which uses the extension register W as the counter.
You interrupt task A in the middle of using the TFM instruction, and switch to
task B. If you use W in task B, when you return to task A the contents of W
will be changed, which will cause malfunction. (Of course, when using the
processor only in single tasking, or if you limit use of the extension
registers to one task only, there is no problem.) Thus, when using the
extension registers in emulation mode, you must not switch tasks without every
time disabling interrupts and saving the extension registers on the stack
before doing starting the new task.
これでは、高速ゲームや OS-9
から拡張レジスタを使いづらいうえ、使いにくい拡張命令も発生します。そのために、拡張レジスタと拡張命令を使うことを前提にしたモード、ネイティブモードが存在します。このモードでのインタラプトは
PC, U, Y, X, DP, W, D, CC
の順にスタックにレジスタを退避して割り込み処理に入ります。ここで注意してほしいのは、
W は DP と D の間にあるということです。これは、 D と W の 32ビットレジスタペア
Q としてスタックに退避するという意味です。
Because of this, not only are
the extension registers difficult to use in high-performance games and OS-9,
but certain instructions also become problematic to use. This is why the
native mode exists as a mode in which the extension registers are assumed to
be in use. In this mode, interrupt processing is entered after saving the
registers on stack in the order PC, U, Y, X, DP, W, D, and CC. What you should
notice here is that W is saved between DP and D. What this means is that D and
W are saved together as the register pair Q.
ネイティブモードの特徴としては、もう１つ、命令のマシンサイクル短縮があげられます。その結果、アドレシングモードによって
20 ~ 35％高速に動作します。
One more feature of native mode is that
instruction machine cycles are shortened. As a result, depending on the
addressing mode, the processor operates 20 to 35% faster.
とくにダイレクト、エクステンド、インヘラント、で顕著[けんちょ=remarkable,
striking, conspicuous]にその効果が現れます。
This effect is particularly
conspicuous in direct, extended, and inherent addressing modes.
--------
７４ Oh!FM
1988-4
p. 74 Oh!FM 1988-4
--------
[Oh!FM 1988-4: p.75]
なお、ネイティブモードでも
V レジスタと MD レジスタはその性格上退避されませんので注意してください。
Take
note that the V and MD registers, due to their nature and expected uses, are
not saved.
エミュレートモードからネイティブモードに移行するには、新設された
MD レジスタのビット 0 (LSB) に 1 を書き込むことによって実現します。
Changing
from the emulation mode to naive mode is accomplished by writing a 1 to bit 0
(LSB) of the newly provided MD register.
さて、 63C09
のモードには上の２つのほかに、 FIRQ
のスタック退避モードが用意されています。ご存知のように、 6809 では FIRQ
をフェッチすると、 PC と CC
のみをスタックに退避してインタラプト処理ルーチンへ分岐します。しかし、制御用のボードマイコンの場合、
FIRQ より IRQ がもう１つあったほうが便利なケースがあります。しかし、 63C09 は
6809
とピンコンパチを[?謳=うた?]っていますので、足の配置を変えるわけにはいきません。そこで、
FIRQ を IRQ
として使用できるように、スタックの退避をすべてのレジスタが行うようにモードをソフトで切り換えられるようになっています。
FIRQ を IRQ として使用する場合は MD レジスタのビット 1 に 1
を書くことによって実現します。
The 63C09 has, in addition to the two
modes mentioned above, modes for saving state to the stack during FIRQ. As you
are know, when the 6809 fetches [sic] a FIRQ, it only saves the PC and CC to
stack before jumping to the interrupt processing routine. However, when
building a single-board controller, there are cases when it is more convenient
to have an extra IRQ than to have a FIRQ. But since the 63C09 asserts pin
compatibility with the 6809, it wouldn't do to change the layout of the chip's
feet. To that purpose, so that the FIRQ can be used as an IRQ, you can make a
software switch to a mode in which the full register set is saved on FIRQ.
When using FIRQ as an IRQ [style interrupt], switch to this mode by writing a
1 to bit 1 of the MD register.
********
トラップ
Traps
63C09
は以下の現象が発生したときにトラップがかかります。
The 63C09 takes a trap
under the following conditions:
１ 未定義命令がフェッチされたとき
２ 除算命令の
DIV 命令で 0 で割ったとき
1: When an unimplemented/undefined instruction
is fetched
2: When a DIV instruction attempts to divide by 0
トラップがかかると、エミュレートモードでは PC, U, Y, X, DP, B,
A, CC の順に、ネイティブモードでは PC, U, Y, X, DP, W, B, A, CC の順に S
レジスタにレジスタをプッシュした後、 $FFF0
のアドレスに書いてあるベクタに分岐します ($FFF0 は 6809 では
RESERVE)。このトラップはリセットの次の割り込み優先度があります。なお、未定義命令かゼロ・ディバイドかを判定する命令として
BITMD 命令があります。
When a trap is taken, after the internal registers
are pushed on the S register in order PC, U, Y, X, DP, B, A, CC in emulation
mode and PC, U, Y, X, DP, W, B, A, CC in native mode, the processor jumps to
the address stored at vector $FFF0 (specified as RESERVED on the 6809). We
have the BITMD instruction to distinguish between an undefined instruction and
a zero divide.
このトラップのため、未定義命令を使っている 6809
のソフトが動作しなくなりますが、代わりに
OS-9/68000等で使われているトラップライブラリを組めるようになります。たとえば、未定義命令に浮動小数点演算プロセッサの呼び出しを割り当てておくと、その命令を未定義命令トラップに引っ掛け、処理ルーチンに飛ばすことが可能になります。このトラップライブラリを利用すると、オブジェクトのサイズをかなり縮められるので便利でしょう。
Because
of these traps, 6809 software that uses undefined instructions will fail to
function. On the other hand, the trap allows trap libraries of the sort that
are used in OS-9/68000 and others. For example, if we allocate calls to a
floating point [co]processor to an unimplemented instruction, when that
unimplemented instruction is trapped, we can use the trap to jump to the
handler routines. Using such a trap library should help significantly reduce
code size.
********
拡張命令
Instruction Extensions
63C09
拡張命令には、既存の命令の対応レジスタを増やした追加命令と新規に設けられた新設命令に分けられます。
663C09
instruction set extensions can be divided into two classes -- additional
versions of existing instructions for working with the added registers, and
entirely new instructions.
新設命令としては、レジスタ間演算命令や、ブロック転送命令、乗算／除算命令、ビット操作命令、ビット演算／転送命令等の命令があります。
The
newly added instructions include register-to-register math, block moves,
multiplication and division, bit operators, and bit math/extraction
instructions.
追加命令
Additional Instructions
~~~~~~~~
63C09
では、既存の命令も拡張されていて、対応するレジスタが増えています。
In the
63C09, some existing instructions have been extended, widening the range of
registers they can operate on.
たとえば、今までありそうでなかった
TSTD, ADCD
などが追加されています。これらは従来でもアセンブラ上でマクロを使って表現できましたが、これらを使うことによりマシンサイクルを短縮できます。
For
example, instructions that seemed like they ought to exist but did not, such
as TSTD and ADCD, have been added. These operations could be expressed in
existing 6809 assembler as macros, but using the new instructions will reduce
machine cycle counts.
また、 ADD や SUB などの命令では、 E/F/W
レジスタが増えたことにより、それに対応する命令が増えています。いわば、 A/B/D
レジスタがもう１組増えたようなもので、プログラミングの柔軟性が増します。ただし、
A/B/D
レジスタで使える命令がすべて対応しているわけではありませんので注意してください（図２）。
In
addition, the number of registers has increased by E/F/W, and versions of
instructions such as ADD and SUB have been added for the new registers. It's
as if another set of the registers A/B/D has been added, and programming
flexibility has improved accordingly. However, you should be aware that not
all instructions that exist for A/B/D have their counterparts for E/F/W.
既存の命令の中で追加の度合いが大きいのは
TFR と EXG 命令でしょう。 TFR, EXG
命令では、対象レジスタの指定にポストバイトのビットパターンを用います。 63C09
ではレジスタが増えていますので、そのビットパターンの組み合わせも増えていて
(0110->W, 0111->V, 1110->E, 1111->F),
レジスタアドレッシングとでもいったらよい状態になっています。このレジスタアドレッシングは新設命令のレジスタ間演算でも使用しています。ここで注意しなければいけないのは、本当の未定義レジスタ番号を指定した場合、
63C09 と 6809 とでは動作が異なるということです。
Among existing
instructions, two that are significantly impacted are TFR and EXG. These both
use a postbyte to specify the registers that will be affected. There are more
registers in the 63C09, so the applicable bit patterns have also increased
(0110->W, 0111->V, 1110->E, 1111->F). These bit patterns might as
well be used in register addressing, and this register addressing is used in
the newly added register-to-register math instructions. Something to be
careful of here is that the results of specifying a register that does not
exist will differ between the 63C09 and the 6809.
図２ アキュムレータで行える処理
Table 2: Operations that can be performed on the accumulator(s)
____________________________________
| A | B | E | F | D | W | Q |
CLR | o | o | o | o | o | o | |
INC | o | o | o | o | o | o | |
DEC | o | o | o | o | o | o | |
TST | o | o | o | o | o | o | |
COM | o | o | o | o | o | o | |
NEG | o | o | | | o | | |
SEX | o*| o*| | | o*| o*| |
ASL/LSL| o | o | | | o | | |
ASR | o | o | | | o | | |
LSR | o | o | | | o | o | |
ROL | o | o | | | o | o | |
LD | o | o | o | o | o | o | o |
ST | o | o | o | o | o | o | o |
ADD | o | o | o | o | o | o | |
SUB | o | o | o | o | o | o | |
CMP | o | o | o | o | o | o | |
ADC | o | o | | | o | | |
SBC | o | o | | | o | | |
AND | o | o | | | o | | |
OR | o | o | | | o | | |
EOR | o | o | | | o | | |
BIT | o | o | | | o | | |
MUL | o*| o*| | | o | | |
DIV | | | | | | | o |
____________________________________
* ワークとして使用
* Used as working registers.
レジスタ間演算命令
Register-to-register Instructions
~~~~~~~~~~~~~~~~~~
6809での演算は、ほとんどレジスタ対メモリないしイミディエイト値で行われていました。そのため
A レジスタと B レジスタの値の AND
をとりたい場合は、どちらかのレジスタをメモリ上にストアしてから演算（この場合は
AND）を行わなければなりませんでした。 63C09
ではこれが解決されていてレジスタ同士の演算が可能になりました。これらは TFR や
EXG と同じレジスタアドレッシングを用います。
Math and logic operations on
the 6809 were mostly performed memory-to-register. Because of that, when you
want to take the AND of register A with register B, you had to store one or
the other register to memory first and then perform the operation (AND in this
case). This is solved in the 63C09 and direct register-to-register math
operations are possible. These use the same register addressing used by TFR
and EXG.
レジスタ間演算命令は以下のようなものがあります。
Register-to-register
operations include the following instructions:
ADDR, ADCR, SUBR,
SBCR,
ANDR, ORR, EORR, CMPR
ブロック転送命令
Block Move/Transfers
~~~~~~~~~~~~~~~~
6809
でメモリ上のデータを移動させるときは、一度そのデータをレジスタにロードしてきては、それをセーブするということを繰り返して行っていました。これはこれでよいのですが、問題はその処理にかかる時間です。そこで
Z80 や 8086 などにもあるブロック転送命令が、 63C09 にも設けられています。
Moving
data in memory with the 6809 involves repeatedly loading part of it into a
register and then saving it. This works, but has the problem of consuming
processing time. This is why the 63C09 includes block moves like such
processors as the Z80 and 8086 have.
--------
Oh!FM 1988-4
７５
Oh! FM 1988-4 p. 75
--------
[Oh!FM 1988-4: p.76]
ブロック転送命令では、転送元アドレス（ソース）、転送先アドレス（ディスティネーション）の指定に
16ビットレジスタの D/X/Y/U/S
レジスタの中から１〜２使います。レジスタの指定にはポストバイトを使い、その形式はレジスタアドレッシングの形式をとります。また、ソースとディスティネーションを同じレジスタでも指定できます。転送するバイト数のカウントには
W レジスタを使います。
As the source and/or destination of block moves,
one or two of the 16-bit registers D/X/Y/U/S can be specified. Register
specification uses a postbyte of the same format as register addressing. The
same register can be specified as both the source and destination. The count
of bytes to transfer is specified by the W register.
転送方法には４種類あり、正方向（TFM
r0+,r1+）/逆方向（TFM r0-,r1-）の通常のブロック転送のほか、 I/O
ポート等のアドレスにデータを次々と流し込むもの（TFM
r0+,r1）、指定ブロックを指定値で塗りつぶすもの（TFM r0,r1+）があります。
There
are four modes of transfer; in addition to forward (TFM r0+,r1+) and reverse
(TFM r0-,r1-), a mode that pours data one byte after another into a single
address such as that of an I/O port (TFM r0+,r1), and a mode that can paint
the specified block of data with a specified value (TFM r0,r1+) [sic].
乗算／除算命令
Multiply/Divide Instructions
~~~~~~~~~~~~~~
6809
には MUL という ８×８ビットの乗算命令がありましたが、これは A レジスタと B
レジスタの値を掛け合わせるだけのものでした。 63C09
で設けられた１６×１６ビット乗算命令（MULD）では、いろいろなアドレシングモードが使え、追加というよりは新設に近いものです。
The
6809 has one 8 by 8 bit multiply instruction, MUL, which can only multiply the
contents of the A and B registers. The 63C09's 16 by 16 bit multiply, MULD,
can use a variety of addressing modes. More than an extension of existing
instructions, it is a newly added instruction.
また、 63C09
にはそれに加えて１６÷８ビット除算（DIVD）、３２÷１６ビット除算（DIVQ）が設けられて、これらも、いろいろなアドレシングモードが使えるようになっています。
Additionally,
the 63C09 has a 16 by 8 bit divide, DIVD, and a 32 by 16 bit divide, DIVQ,
both of which can use a variety of addressing modes.
ビット操作命令（6301 コンパチ命令）
Bit [Pattern] Operation (6301
Compatibility) Instructions
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
日立の
HD6301 には、 6801 の拡張命令としてビット操作命令が新設されていましたが、同じ
63 シリーズの 63C09
にも同じ命令があります。これらの命令はイミディエイトデータとメモリの内容を論理演算して、結果をメモリに戻したり、関連コンディションコードを変化させてしまうので、ビットパターンを操作するときなどに重宝します。
Hitachi's
HD6301 has, as extensions to the 6801 instruction set, new bit operation
instructions. The 63C09, a member of the same 63 series, has the same. These
instructions are of great value, performing logical operations directly
between memory and immediate data, returning the results to memory, and
setting the relevant condition codes accordingly.
行える論理演算には、論理積（AIM）、論理和（OIM）排他的論理和（EIM）、論理積コンディションコード（TIM）があります。オブジェクトの構成は、
＜命令コード＞、＜ビットの位置＞、＜オペランド＞
の順になっています。
Operations
available are logical _and_ (AIM), logical _or_ (OIM), logical _exclusive_or_
(EIM), and bit test-to-condition-codes (TIM). The object code has the
structure
<op-code>, <bit position> [sic:
pattern], <operand>
in that order.
これらの命令を使うと、
6301 の命令はマクロアセンブラを用いれば 63C09 上で実行可能になります。つまり
OASYS Lite 等の組み込みプログラムを FM
上で動かすことができるかも知れないわけで、そういう意味でも美味しい命令なのです（もっとも、その前に根性で
ROM を逆アセンブルしなければなりませんが）。
Using these instructions, it
becomes possible by means of a macro-assembler to execute 6301 instructions on
the 63C09. In other words, it may be possible to run embedded [sic] software
such as OASYS Lite programs. In this sense, these are very tasty instructions.
(Of course, you'll first have to get tough and disassemble the ROM.)
ビット演算／転送命令
Bit Calculation/Extraction Instructions
~~~~~~~~~~~~~~~~~~~~
63C09
には、多分に I/O
を意識したビット演算／転送命令が存在しています。これらの命令は、アドレシングモードにダイレクトモードしかサポートしていない難はありますが、使い慣れれば便利に使えるでしょう。動作は、ダイレクトページの
LABEL のビット n と REG レジスタのビット m を論理演算して、 REG
レジスタに入れるものがほとんどです。ビット演算／転送命令には以下のようなものがあります。
The
63C09 has [individual] bit calculation and extraction instructions, probably
intended for I/O. These instructions have the deficiency of only supporting
direct mode addressing, but with a little practice, should be useful. They
perform logical operations on bit n of direct mode address LABEL and bit m of
register REG, most of them leaving their result in REG. The following bit
calculation/extraction instructions are supported:
BAND, BOR,
BEOR, BIAND,
BIOR, BIEOR, LDBT, STBT
オブジェクトの構成は
＜命令コード
($11,$xx)＞、＜ポストバイト＞、＜オペランド＞
と、かなり変則な構成をとります。オペランドはダイレクトアドレシングのみです。また、ポストバイトは特殊な形式をとります。
Object
code follows the following rather irregular structure:
<op-code
($11,$xx)>, <post-byte>, <operand>
The operand is
direct page addressing only, and the post-byte has its own peculiar format.
[Note that the post-byte format is not explained further in the article.
Again, see DeKok and Simpson's technical pages at
http://www.sandelman.ottawa.on.ca/People/Alan_DeKok/interests/6309.techref.html
.]
その他の命令
Other Instructions
~~~~~~~~~~~~
その他の命令としては、先ずモード切り換え命令があります。といっても、エミュレートモードからネイティブモードへの移行は、
MD レジスタのビット 0 (LSB) に１を書き込むことによって行われますので、 MD
レジスタに対する普通の LD 命令を使います。
Among the other instructions
is the mode change instruction mentioned above. Or, rather, shifting from
emulation mode to native mode is accomplished by writing a 1 to bit 0 of the
MD register, just using the LD for the MD register.
次にトラップがかかったとき、未定義命令でかかったのか除算のエラーで起こったのかを調べる命令
BITMD があります。これは、 MD レジスタのステータスビット（ビット 7 or
6）を調べ、どちらでトラップがかかったのかを知らせます。ただし、この命令を実行すると
MD レジスタのステータスビット（ビット 7 and
6）はクリアされますので、未定義コードトラップか、 Divide by Zero
トラップかは、一度きりしか調べることはできません。
Next, when a trap is
taken, to determine whether the source of the trap was an unimplemented
instruction or a divide error, we have BITMD. This investigates the status
bits (bit 7 or 6) to tell us the cause of the trap. However, when you execute
this instruction, the status bits (bits 7 and 6) are cleared so you can only
check whether the source was the undefined instruction trap or the Divide by
Zero trap once.
そして、スタックに関するものがあります。 63C09
ではレジスタが増設されていますが、現在の PSHS/PSHU
ではそれらをスタックにセーブすることはできません。なぜなら、PSHS/PSHU および
PULS/PULU
のポストバイトが、すでにすべて割り当てられていて追加の余地がないということです。そこで、
63C09 では増設されたレジスタへのスタック操作は別命令の
Finally, we have
stack instructions. The 63C09 has additional registers, but the original
PSHS/PSHU cannot be used to save any of them. The post-byte for PSHS/PSHU and
PULS/PULU is already completely allocated, leaving no room for additional
registers. For that purpose, the 63C09 has the following new stack
instructions:
PSHSW, PULSW, PSHUW, PULUW
を使います。ただし、これは
W
レジスタに対するもののみしかありません。よって、これらはポストバイトをもたないインヘレンとアドレシングのみです。
But
there are only stack instructions for the W register, so these instructions
operate in inherent mode and do not have a post-byte.
********
おわりに
Wrapping Up
以上 63C09
に隠されていた機能の大筋を説明してきました。 6809
に＋αで追加してほしかった機能がほぼ盛り込まれており、
6809派にはひさびさの好ニュースといえます。ただ、惜しむらくは登場時期が遅かったことで、そのため活躍の場がパソコンの改造か、産業用ワンボードマイコン程度に限られてしまったことです。ゲームパソコンも
68000系や 8086系、 65816 といった１６ビットＣＰＵを使い始めている現状では、
63C09
を積んだパソコンをメーカーが出荷することは、まずありえないことでしょう。当面は市場アプリに依存しない
FM-11等の改造にしか使えないというのは残念なことです。
We have given a
general outline of the hidden functionality of the 63C09 above. It contains a
wealth of 6809-plus-alpha extensions, and is a bit of welcome, if long-awaited
news for fans of the 6809. But it is regretable that the news is rather
untimely, and the places where it can be put to good use are now pretty much
limited to customizing existing personal computers and designing industrial
one-board microcomputers. In the current market where game computers are now
moving on to the 68000, 8086, and 65816 class 16-bit CPUs, there really won't
be any personal computer shipping with a 63C09. It is unfortunate that the
only place to really use it now is in customizing such computers as the FM-11,
which do not have to depend on packaged applications from the marketplace.
なお、この稿をまとめるにあたっては、私が解析した資料のほか、
63C09 解析委員会の仲間（とくに Gigo氏と
Miyazaki氏）が解析された資料を参照させていただきました。 63C09
解析委員会関係者のご協力に感謝いたします。
In addition to material I have
produced myself, I have referenced material produced by members of the 63C09
Survey Committee (especially Mr. Gigo and Mr. Miyazaki). I offer my gratitude
for the cooperation of all who have participated in the 63C09 Survey
Committee.
[Translator's note: Not having any clues about gender, I am by default
assuming Gigo-shi and Miyazaki-shi are male -- I could well be wrong.]
--------------------------------
＜参考文献＞
<References>
・63C09解析委員会、「お年玉プレゼント
63C09 に隠し機能があった」など、ＮＡＮＮＯ−ＮＥＴ、1988年１月１日〜
*
63C09 Survey Committee -- "A New Years Gift: There hidden functions in the
63C09" and other material on NANNO-NET, from Jan 1, 1988.
・モトローラ、「MC6809-MC6809Eマイクロプロセッサプログラミングマニュアル」、ＣＱ出版、1982年
*
Motorola, MC6809-MC6809E Microprocessor Programming Manual [Japanese
edition], CQ Shuppan [CQ Publishing], 1982
・「6809
インストラクションポケットブック」、Oh!FM 1983年第４号、日本ソフトバンク
*
"6809 Instruction Pocket Reference", Oh!FM 1983-4, Softbank Japan
・水谷隆太、「6809の未定義命令」、I/O
1985年５月号、工学社
* Mizutani, Ryūta, "6809 Undefined Instructions",
I/O, May 1985, Kohgakusha
・原進、「FM-11 のクロックを 3MHz
に」、パソコンワールド 1987年１月号、ピーシーワールドジャパン
* Hara,
Susumu, "Overclocking the FM-11 to 3MHz", Pasokon World, Jan 1987,
P-C-World Japan
[Note: Probably not the current PCWorld founded in 1995.]
--------
７６ Oh!FM 1988-4
p. 76 Oh!FM 1988-4
--------
[Oh!FM
1988-4: p.77]
図３ 63C09で増えた命令（灰色に塗られた部分[=>*囲*]）
Table 3:
Instruction Extensions for the 63C09 (extensions in gray)
[In the original, the extensions were shown in gray background. Here I have
put asterisks around them.]
（
横の列は、上からプリバイトなし、プリバイト
$10付き、フリバイト $11付きの順に並んでいる。また、
Rows in the following
order: without pre-byte, with $10 pre-byte, and with $11 pre-byte. Also
各項目中の下段左側の数値はサイクル数で、カッコ内がネイティブモード時の値。右側は命令長。
on
the second line of each entry, the left number is the cycle count, with native
cycle count in parenthesis. The right number is the byte count.
）
[原稿の編集に因る誤植在り。 Original contains typographical errors.]
[The
only Japanese word in the table is 「（なし）」 {"(nashi)" => "(none)"},
so it makes no real sense to repeat the table for each language. Refer to
the transcription at
https://defining-computers.blogspot.com/2022/05/transcription-of-article-on-63c09-in-oh-fm-1988-4-72.html
if necessary.]
=================================================================================================================================================================|
| DIRECT | | | REL |ACC A/D/E|ACC B/W/F| INDEXD | EXTEND | IMMED | DIRECT | INDEXD | EXTEND | IMMED | DIRECT | INDEXD | EXTEND |
|0000xxxx|0001xxxx|0010xxxx| 0011xxxx | 0100xxxx| 0101xxxx| 0110xxxx|0111xxxx|1000xxxx|1001xxxx| 1010xxxx|1011xxxx|1100xxxx|1101xxxx| 1110xxxx|1111xxxx|
| 0x | 1x | 2x | 3x | 4x | 5x | 6x | 7x | 8x | 9x | Ax | Bx | Cx | Dx | Ex | Fx |
=================================================================================================================================================================|
0000 0 | NEG | (PRE) | BRA | LEAX | NEGA | NEGB | NEG | NEG | SUBA | SUBA | SUBA | SUBA | SUBB | SUBB | SUBB | SUBB |
(none) | 6(5),2 | (BYTE1)| 3,2 | 4+,2+ | 2(1),1 | 2(1),1 | 6+,2+ | 7(6),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* addr *|* negd *| | | |* subw *|* subw *|* subw *|* subw *| | | | |
($10) | | | | 4,3 | 3(2),2) | | | | 5(4),4 | 7(5),3)|7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* band *| | | | |* sube *|* sube *|* sube *|* sube *|* subf *|* subf *|* subf *|* subf *|
($11) | | | | 7(6),4 | | | | | 3,3 | (4),3 | 5+,3+ | 6(5),4 | 3,3 | 5(4),3 | 5+,3+ | 6(5),4 |
=================================================================================================================================================================|
0001 1 |* oim *| (PRE) | BRN | LEAY | | |* oim *|* oim *| CMPA | CMPA | CMPA | CMPA | CMPB | CMPB | CMPB | CMPB |
(none) | 6,3 | (BYTE2)| 3,2 | 4+,2+ | | | 7+,3+ | 7,4 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBRN |* adcr *| | | | |* cmpw *|* cmpw *|* cmpw *|* cmpw *| | | | |
($10) | | | 5,4 | 4,3 | | | | | 5(4),4 | 7(5),3)|7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* biand *| | | | |* cmpe *|* cmpe *|* cmpe *|* cmpe *|* cmpf *|* cmpf *|* cmpf *|* cmpf *|
($11) | | | | 7(6),4 | | | | | 3,3 | 5(4),3 | 5+,3+ | 6(5),4 | 3,3 | 5(4),3 | 5+,3+ | 6(5),4 |
=================================================================================================================================================================|
0010 2 |* aim *| NOP | BHI | LEAS | | |* aim *|* aim *| SBCA | SBCA | SBCA | SBCA | SBCB | SBCB | SBCB | SBCB |
(none) | 6,3 | 2(1),1 | 3,2 | 4+,2+ | | | 7+,3+ | 7,4 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBHI |* subr *| | | | |* sbcd *|* sbcd *|* sbcd *|* sbcd *| | | | |
($10) | | |5/6(5),4| 4,3 | | | | | 5(4),4 | 7(5),3)|7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* bor *| | | | | | | | | | | | |
($11) | | | | 7(6),4 | | | | | | | | | | | | |
=================================================================================================================================================================|
0011 3 | COM | SYNC | BLS | LEAU | COMA | COMB | COM | COM | SUBD | SUBD | SUBD | SUBD | ADDD | ADDD | ADDD | ADDD |
(none) | 6(5),2 | 2,1 | 3,2 | 4+,2+ | 2(1),1 | 2(1),1 | 6+,2+ | 7(6),3 | 4(3),3 | 6(4),2 |6+(5+),2+| 7(5),3 | 4(3),3 | 6(4),2 |6+(5+),2+| 7(5),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBLS |* sbcr *|* comd *|* comw *| | | CMPD | CMPD | CMPD | CMPD | | | | |
($10) | | |5/6(5),4| 4,3 | 3(2),2 | 3(2),2 | | | 5(4),4 | 7(5),3)|7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* bior *|* come *|* comf *| | | CMPU | CMPU | CMPU | CMPU | | | | |
($11) | | | | 7(6),4 | 3(2),2 | 3(2),2 | | | 5(4),4 | 7(5),3)|7+(6+),3+| 8(6),4 | | | | |
=================================================================================================================================================================|
0100 4 | LSR | sexw | BHS/BCC| PSHS | LSRA | LSRB | LSR | LSR | ANDA | ANDA | ANDA | ANDA | ANDB | ANDB | ANDB | ANDB |
(none) | 6(5),2 | 4,1 | 3,2 | 5+(4+),2 | 2(1),1 | 2(1),1 | 6+,2+ | 7(6),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | |LBHS/BCC|* andr *|* lsrd *|* lsrw *| | |* andd *|* andd *|* andd *|* andd *| | | | |
($10) | | |5/6(5),4| 4,3 | 3(2),2 | 3(2),2 | | | 5(4),4 | 7(5),3)|7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* beor *| | | | | | | | | | | | |
($11) | | | | 7(6),4 | | | | | | | | | | | | |
=================================================================================================================================================================|
0101 5 | eim | | BLO/BCS| PULS | | |* eim *|* eim *| BITA | BITA | BITA | BITA | BITB | BITB | BITB | BITB |
(none) | 6,3 | | 3,2 | 5+(4+),2 | | | 7+,3+ | 7,4 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | |LBLU/BCS|* orr *| | | | |* bitd *|* bitd *|* bitd *|* bitd *| | | | |
($10) | | |5/6(5),4| 4,3 | | | | | 5(4),4 | 7(5),3 |7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* bieor *| | | | | | | | | | | | |
($11) | | | | 7(6),4 | | | | | | | | | | | | |
=================================================================================================================================================================|
0110 6 | ROR | LBRA | BNE | PSHU | RORA | RORB | ROR | ROR | LDA | LDA | LDA | LDA | LDB | LDB | LDB | LDB |
(none) | 6(5),2 | 5(4),3 | 3,2 | 5+(4+),2 | 2(1),1 | 2(1),1 | 6+,2+ | 2,2 | 7(6),3 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBNE |* eorr *|* rord *|* rorw *| | |* ldw *|* ldw *|* ldw *|* ldw *| | | | |
($10) | | |5/6(5),4| 4,3 | 3(2),2 | 3(2),2 | | | 4,4 | 6(5),3 | 6+,3+ | 7(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* ldbt *| | | | |* lde *|* lde *|* lde *|* lde *|* ldf *|* ldf *|* ldf *|* ldf *|
($11) | | | | 7(6),4 | | | | | 3,3 | 5(4),3 | 5+,3+ | 6(5),4 | 3,3 | 5(4),3 | 5+,3+ | 6(5),4 |
=================================================================================================================================================================|
0111 7 | ASR | LBSR | BEQ | PULU | ASRA | ASRB | ASR | ASR | | STA | STA | STA | | STB | STB | STB |
(none) | 6(5),2 | 9(7),2 | 3,2 | 5+(4+),2 | 2(1),1 | 2(1),1 | 6+,2+ | 7(6),3 | | 4(3),2 | 4+,2+ | 5(4),3 | | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBEQ |* cmpr *|* asrd *| | | | |* stw *|* stw *|* stw *| | | | |
($10) | | |5/6(5),4| 4,3 | 3(2),2 | | | | | 6(5),3 | 6+,3+ | 7(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* stbt *| | | | | |* ste *|* ste *|* ste *| |* stf *|* stf *|* stf *|
($11) | | | | 8(7),4 | | | | | | 5(4),3 | 5+,3+ | 6(5),4 | | 5(4),3 | 5+,3+ | 6(5),4 |
=================================================================================================================================================================|
1000 8 | ASL/LSL| | BVC | |ASLA/LSLA|ASLB/LSLB| ASL/LSL | ASL/LSL| EORA | EORA | EORA | EORA | EORB | EORB | EORB | EORB |
(none) | 6(5),2 | | 3,2 | | 2(1),1 | 2(1),1 | 6+,2+ | 7(6),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBVC |* pshsw *|* asld *| | | |* eord *|* eord *|* eord *|* eord *| | | | |
($10) | | |5/6(5),4| 5/6,2 | 3(2),2 | | | | 5(4),4 | 5(5),3 |7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |*tfm(r+,r+)*| | | | | | | | | | | | |
($11) | | | | 6+3n,3 | | | | | | | | | | | | |
=================================================================================================================================================================|
1001 9 | ROL | DAA | BVS | RTS | ROLA | ROLB | ROL | ROL | ADCA | ADCA | ADCA | ADCA | ADCB | ADCB | ADCB | ADCB |
(none) | 6(5),2 | 2(1),1 | 3,2 | 5(4),1 | 2(1),1 | 2(1),1 | 6+,2+ | 2,2 | 7(6),3 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBVS |* pulsw *|* rold *|* rolw *| | |* adcd *|* adcd *|* adcd *|* adcd *| | | | |
($10) | | |5/6(5),4| 6,2 | 3(2),2 | 3(2),2 | | | 5(4),4 | 7(5),3 |7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |*tfm(r-,r-)*| | | | | | | | | | | | |
($11) | | | | 6+3n,3 | | | | | | | | | | | | |
=================================================================================================================================================================|
1010 A | DEC | ORCC | BPL | ABX | DECA | DECB | DEC | DEC | ORA | ORA | ORA | ORA | ORB | ORB | ORB | ORB |
(none) | 6(5),2 | 3(2),2 | 3,2 | 3(1),1 | 2(1),1 | 2(1),1 | 6+,2+ | 7(6),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBPL |* pshuw *|* decd *|* decw *| | |* ord *|* crd *|* ord *|* ord *| | | | |
($10) | | |5/6(5),4| 6,2 | 3(2),2 | 3(2),2 | | | 5(4),4 | 7(5),3 |7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* tfm(r+,r)*|* dece *|* decf *| | | | | | | | | | |
($11) | | | | 6+3n,3 | 3(2),2 | 3(2),2 | | | | | | | | | | |
=================================================================================================================================================================|
1011 B |* tim *| | BMI | RTI | | |* tim *|* tim *| ADDA | ADDA | ADDA | ADDA | ADDB | ADDB | ADDB | ADDB |
(none) | 4,3 | | 3,2 | 6/15(17),1 | | | 5+,3+ | 5,4 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 | 2,2 | 4(3),2 | 4+,2+ | 5(4),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBMI |* puluw *| | | | |* addw *|* addw *|* addw *|* addw *| | | | |
($10) | | |5/6(5),4| 4,3 | | | | | 5(4),4 | 7(5),3 |7+(6+),3+| 8(6),4 | | | | |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* tfm(r,r+)*| | | | |* adde *|* adde *|* adde *|* adde *|* addf *|* addf *|* addf *|* addf *|
($11) | | | | 6+3n,3 | | | | | 3,3 | 5(4),3 | 5+,3+ | 6(5),4 | 3,3 | 5(4),3 | 5+,3+ | 6(5),4 |
=================================================================================================================================================================|
1100 C | INC | ANDCC | BGE | CWAI | INCA | INCB | INC | INC | CMPX | CMPX | CMPX | CMPX | LDD | LDD | LDD | LDD |
(none) | 6(5),2 | 3(2),2 | 3,2 | 20(22),2 | 2(1),1 | 2(1),1 | 6+,2+ | 7(6),3 | 4(3),3 | 6(4),2 |6+(5+),2 | 7(5),3)| 3,3 | 5(4),2 | 5+,2+ | 6(5),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBGE | |* incd *|* incw *| | | CMPY | CMPY | CMPY | CMPY | |* ldq *|* ldq *|* ldq *|
($10) | | |5/6(5),4| | 3(2),2 | 3(2),2 | | | 5(4),4 | 7(5),3 |7+(6+),3+| 8(6),4 | | 8(7),3 | 8+,3+ | 9(8),4 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* BITMD *|* ince *|* incf *| | | CMPS | CMPS | CMPS | CMPS | | | | |
($11) | | | | 4,3 | 3(2),2 | 3(2),2 | | | 5(4),4 | 7(5),3 |7+(6+),3+| 8(6),4 | | | | |
=================================================================================================================================================================|
1101 D | TST | SEX | BLT | MUL | TSTA | TSTB | TST | TST | BSR | JSR | JSR | JSR |* ldq *| STD | STD | STD |
(none) | 6(4),2 | 2(1),1 | 3,2 | 11(10),1 | 2(1),1 | 2(1),1 |6+(5+),2+| 7(6),3 | 7(6),2 | 7(6),2 | 7+(6+),2| 8(6),4 | 5,5 | 5(4),2 | 5+,2+ | 6(5),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBLT | |* tstd *|* tstw *| | | | | | | |* stq *|* stq *|* stq *|
($10) | | |5/6(5),4| | 3(2),2 | 3(2),2 | | | | | | | | 8(7),3 | 8+,3+ | 9(8),4 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | |* ldmd *|* tste *|* tstf *| | |* divd *|* divd *|* divd *|* divd *| | | | |
($11) | | | | 5,3 | 3(2),2 | 3(2),2 | | | 25,3 |27(26),3| 27+,3+ |28(27),4| | | | |
=================================================================================================================================================================|
1110 E | JMP | EXG | BGT | | | | JMP | JMP | LDX | LDX | LDX | LDX | LDU | LDU | LDU | LDU |
(none) | 3(2),2 | 8(5),2 | 3,2 | | | | 3+,2+ | 4(3),3 | 3,3 | 5(4),2 | 5+,2+ | 6(5),3 | 3,3 | 5(4),2 | 5+,2+ | 6(5),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBGT | | | | | | LDY | LDY | LDY | LDY | LDS | LDS | LDS | LDS |
($10) | | |5/6(5),4| | | | | | 4,4 | 6(5),3 |6+(6+),3+| 7(6),4 | 4,4 | 6(5),3 |6+(6+),3+| 7(6),4 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | | | | | | |* divq *|* divq *|* divq *|* divq *| | | | |
($11) | | | | | | | | | 34,4 |36(35),3| 36+,3+ |37(36),4| | | | |
=================================================================================================================================================================|
1111 F | CLR | TFR | BLE | SWI | CLRA | CLRB | CLR | CLR | | STX | STX | STX | | STU | STU | STU |
(none) | 6(5),2 | 6(4),2 | 3,2 | 19(21),1 | 2(1),1 | 2(1),1 | 6+,2+ | 7(6),3 | | 5(4),2 | 5+,2+ | 6(5),3 | | 5(4),2 | 5+,2+ | 6(5),3 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | LBLE | SWI2 |* clrD *|* clrw *| | | | STY | STY | STY | | STS | STS | STS |
($10) | | |5/6(5),4| 20(22),2 | 3(2),2 | 3(2),2 | | | | 6(5),3 |6+(6+),3+| 7(6),4 | | 6(5),3 |6+(6+),3+| 7(6),4 |
--------|--------|--------|--------|------------|---------|---------|---------|--------|--------|--------|---------|--------|--------|--------|---------|--------|
| | | | SWI3 |* clre *|* clrf *| | |* muld *|* muld *|* muld *|* muld *| | | | |
($11) | | | | 20(22),2 | 3(2),2 | 3(2),2 | | | 28,4 |30(29),3| 30+,3+ |31(30),4| | | | |
=================================================================================================================================================================|
[** These are the typographical errors I noticed in the above table: ]
[** Several other places appear to be errors and need to be checked.]
[*1* Cycle count for sube direct mode ($1190) is clearly a typo, see subf: (4),3 => 5(4),3 .]
[*2* Long branches with dual mnemonics (LBHS/LBCC=$1024 and LBLO/LBCS=$1025) abbreviate the second mnemonic in the original to fit the table.]
[*3* First mnemonic (LBLU) for LBLO/LBCS ($1025) is a typo.]
[*4* The cycle and byte counts for ROR extended ($76) and LDA immediate ($86) are swapped: ROR extended => 7(6),3 and LDA immediate => 2,2 .]
[*5* The byte count for LBSR ($17) is a typo: 2=>3 .]
[*6* The cycle and byte counts for ROL extended ($79) and ADCA immediate ($89) are swapped: ROL extended => 7(6),3 and ADCA immediate => 2,2 .]
[*7* The mnemonic for (crd) for ord direct ($109A) is a typo.]
[*8* The cycle and byte counts for puluw ($103B) appear to be a typo.]
[*9* The byte count for CMPX indexed ($AC) is a typo: 2=>2+ .]
[*10* The op-code at which ldq immediate is shown ($CD) looks maybe out-of-place (=>$10CC?), needs to be checked.]
[*11* The cycle counts for LDY, STY, LDS, and STS indexed ($10AE, $10EE, $11AE, $11EE) look odd: 6+(6+), need to be checked.]
[*12* The mnemonic for clrd ($104F) is a typo: clrD .]
--------
Oh!FM 1988-4 ７７
Oh! FM 1988-4 p. 77
[Google Translate output below (Yes, it turns into mush pretty quick.):]
16-bit multiplication / division / register-to-register operation / block
transfer is possible
Super 8-bit class MPU
Search for extended
functions of 63C09
63C09 Analysis Committee UNO
There is an
LSI called 63C09 in the minor change version of 6809. Some users who are
strong in hardware have bought the high speed and used it to modify the main
body. However, I recently found out that various extensions were hidden in
this 63C09. Here, we would like to ask the "63C09 Analysis Committee" who has
discovered and explored these functions to report the outline.
In
addition, if the main body is modified, especially the CPU is replaced, the
manufacturer's repair is not guaranteed, and other peripheral LSIs and
peripheral devices may have to be replaced. In addition, 63C09 is a part of
the conventional software (6C09). Or many) may not work, so I would not
recommend it to anyone other than those who are very confident in their
skills, such as "I only use my own programs!".
******************
High-speed
version of 6809 63C09
There are various ways to enjoy a personal
computer, but there is a hardware modification as a play that is only allowed
for the soldiers of that line. Various modifications have been made since
ancient times, but among them, the speedup of the CPU is widespread among
program self-made groups who do not care about commercial software because the
processing power is significantly improved and it can be done relatively
easily. It has been tried. In the old days, he changed his 68A09 (1.2 MHz)
loaded on FM-8 to 68B09 (2 MHz) and gave it the same processing speed as FM-7.
Clocking up and running at 2.5-4 MHz is a typical example.
Some
people may think, "Well, 2.5 ~ 4MHz was such a fast 6809", but it actually
exists. Hitachi's 63C09 MPU sold at chip stores in Akihabara and Nihonbashi is
the C-MOS version of the 6809, which runs at 3 MHz. If you follow the normal,
he will have 1.5 times the processing power of 68B09 (2 MHz), and if you
select and use the one that operates at 4 MHz, which is out of the standard,
it will be twice the processing power.
He uses the 63C09 to speed
things up, so it's basically as simple as swapping the CPU and clock, but
sometimes that's not enough. For models such as FM-8, 7, 77D1 / D2 / L4, 77AV,
11 where the CPU is plugged into the socket, simply replace it, but like
FM-NEW7, 77AV20 / 40 / 20EX / 40EX. For models that are soldered directly to
the board, the CPU will not pull out unless you have a considerable amount of
skill. Also, if the clock is up, peripheral LSIs and peripheral devices may
not be able to catch up, in which case they must be replaced, but it will be
difficult if custom LSIs are frequently used such as AV systems. It is quite
difficult to clock up with a 7 / AV system that operates at a delicate timing,
and even though the clock is up, the built-in timer and software timing are
used for protection and other processing at the end. Most of the commercially
available application software will be useless.
By the way, the
speedup is accompanied by these various difficulties, but the result is more
than compensated for the hardship.
By the way, taking the case of
FM-11 as an example, it seems that the limit is about 2.5 to 3 MHz if only the
CPU is replaced, and if you want more than that, it seems that you need to
replace some peripheral LSIs. The 11 can also speed up the subsystem, up to 4
MHz with some modifications. In particular, the display speed of his FM-11
subsystem, which has been converted to 4 MHz, is remarkable, and the display
speed of Chinese characters is not much different from that of FM16β, which
has a Chinese character VRAM.
*************
Discovery of
extensions
So, the veteran heroes around me made speedup
improvements to his FM-11 one after another, but there was one strange
problem.
Comas word processor WPV3 has stopped working. At first I
thought it was a soft timing issue or something mentioned above, but to my
surprise, he dropped the clock to 2 MHz and it didn't work.
Then,
the cause investigation began with his friend Gigo as the center, but soon it
turned out that he was caught by an undefined order of 6809. An undefined
instruction is an instruction that is not defined in the manual published by
the manufacturer, and although it is supposed that even if such an instruction
is used, it does not work at all, but it is actually hidden. Sometimes it is
an order. A long time ago, computer magazines often contained analysis
articles on hidden instructions of CPUs made by various companies. like
this
--------
72 Oh! FM 1988-4 Warning: If you replace the CPU
with 63C09, a lot of commercial applications (especially games) will not
work.
--------
[Oh! FM 1988-4: p.73]
There was a hidden
order in 6809, though it wasn't that big of a deal. Now, the fact that he
treats undefined instructions differently between 63C09 and 6809 means that
hidden instructions may also be different. Considering the shipping start time
of 63C09 (Autumn 1985), it was natural that some functions were added, and I
was expecting "maybe".
One of the code that was stuck was "$ 1F, $
62". The instruction itself is familiar to him in his TFR (data transfer
instruction between registers), but he is instructed to transfer from an
undefined register to the Y register. In the case of 6809, $ FFFF is returned
in the Y register because it is undefined, but in the case of 63C09, the Y
register contains a messed up [value]. As an attempt, when I transferred the
data from the Y register to the undefined register number and then returned
from the undefined register number to the Y register, the original data
remained properly ... In other words, the undefined register number in 63C09
wasn't too undefined, it was a number pointing to a real register!
Discovering
the hidden register, his Gigo was ecstasy and ecstasyly called his friend. And
it was too late for me at night [dead of the night] ... The content of the
story is "63C09 has an extra register. There must be an instruction because
there is a register. Let's find out by hand with everyone", then the day to
search for hidden instructions begins, and the disassembly table The
monotonous task of writing unallocated code in memory with a debugger, setting
breakpoints, setting values in registers with TFR and executing them, and
looking at the contents of the registers was repeated. While exchanging
information on the results found that day through personal computer
communication, enthusiasts who are doing his OS-9 on FM-11, which is almost
sick, gathered, "63C09 Analysis Committee" Group naturally occurred.
Mania's
obsession was horrifying, and soon the outline of his 36C09 extension was
revealed. To outline
・ Three types of registers have been added, one of
which can be used as an accumulator and index register.
・ Instructions
such as 32 ÷ 16 bit division, 16 ÷ 8 bit division, 16 × 16 bit multiplication,
register-to-register operation, bit operation, and block transfer have been
expanded.
・ Trap is applied when an undefined instruction is
detected.
・ It has two operation modes, 6809 compatible mode and 63C09
original mode.
By the way, he has improved the inconveniences and
weaknesses of the 6809 considerably, and also includes powerful functions that
do not seem to be an 8-bit MPU.
These analysis results have been
uploaded to several BBSs, starting with NANNO-NET. We received a lot of
feedback from many networkers, but in order for more people to know the whole
picture of "8-bit MPU over 8 bits" 63C09 [zenbo = entire body], Oh! FM I will
borrow it from the magazine and report it.
*******************
63C09
merit
and demerit
The HD63C09 sold by Hitachi is Motorola's MC6809 and
pin-compatible 8-bit MPU. The MPU specification is a form of the 6809 with
extensions added, and is a high-level compatibility of the 6809 (except for
undefined instructions). Although it has not been officially announced by
Hitachi, the processing power of the 6809 PC can be greatly improved by taking
advantage of the extended functions of the 63C09.
The merit of
replacing the MPU of the 6809 personal computer with 63C09 is the improvement
of processing capacity. The following three points can be considered as the
factors.
1 High-speed clock
2 Extension instruction /
extension register
3 Native mode
1 is a matter of course, and
if you raise the operating clock of the MPU, the execution speed of the
software will increase. Conventional software can be operated at high speed,
except for some parts that are caught due to undefined instruction traps and
software timers. The rate of increase of the operating clock varies depending
on the hardware, and in some cases it can hardly be increased.
2 is
effective when writing new software or applying a patch to existing software.
With the conventional 6809, the equivalent of the processing expressed by the
macro function of the assembler can now be written with one instruction of his
63C09, and the machine cycle can be shortened.
3 is caused by the
instruction execution cycle being shorter than in the normal emulation mode
when switching to the 63C09 specific mode. Using this mode, even with the same
operating clock, the execution speed will be up to 20 to 30% faster than usual
(the effect will differ depending on the addressing mode). However, there are
differences in operation due to stacking and interrupts, so in order to use
native mode, it is necessary to rewrite a part of the system such as F-BASIC
or his OS-9.
On the contrary, the disadvantages are that not only
the software that uses the undefined instructions of 6809 but also the
commercial software that uses many built-in timers and others will
malfunction, and the extended function of 63C09. In order to utilize them, it
is necessary to have a certain level of skill to create development tools to
utilize them, and it can be said that the difficulty for Novice is that it is
difficult.
Comparing the merits and demerits, at present, people
who just lack the program can benefit from it, but ordinary game users and app
users should never touch it.
Then, I will explain the extended
functions of 63C09 in order below.
************
Expansion register
In 63C09, the number of
registers has increased by 3 from 6809 (Fig. 1). Two are 16-bit registers and
the other is an 8-bit mode status register.
W register [16
bits]
~~~~~~~~~~~~~~~~~~~~
A 16-bit register that can be used both
as an accumulator and as an index register.
When used as an
accumulator, 16 bits
--------
Oh! FM 1988-4 73
--------
[Oh!
FM 1988-4: p.74]
It can also be used as a register by dividing it
into two 8-bit registers (E / F registers). It's just like adding another set
of existing D / A / B registers. However, some instructions, such as AND / OR,
cannot be used with W / E / F registers.
Also, it can be used as a
32-bit register (Q register) by concatenating it with the existing D register,
and is used for multiplication and division.
When using it as an
index register, use it in the same way as the existing X / Y register. In this
case, use a bit pattern that was not used for postbytes in 6809. There is no
accumulator offset, 5-bit offset, or 8-bit constant offset when using the W
register as an index register.
Also, as a characteristic usage,
there is a method of using it as a counter register in block transfer.
V
register [16 bits]
~~~~~~~~~~~~~~~~~~~~
Instructions that use the V
register are limited to inter-register operation instructions and TFR. The
feature of the V register is that the value of the register does not change
even if the MPU is reset. This register will be useful for the purpose of
holding constants etc. in the OS etc.
MD register [8 bits] ~~~~~~~~~~~~~~~~~~~~ Abbreviation for mode / status bit register, which is used to display the modes and statuses that have increased in 63C09, such as error detection during division execution, operation check of undefined instruction traps, and operation mode settings. The meaning of each bit is as follows: ・ 1 is set when bit 7 R division is divided by 0 ・ Bit 6 R 1 is set when fetching an undefined instruction ・ Bit 1 W Register save mode setting bit during FIRQ At 0-> FIRQ, only PC to CC is saved to the stack Evacuate all registers at 1-> FIRQ ・ Bit 0 W Operation mode setting bit 0-> emulated mode 1-> Native mode At reset, all bits are set to 0.
Figure 1 63C09 register configuration
__________________________________________________
|
---------- Q ---------- |
| ---- D ---- | | ---- W ---- |
| -A- | |
-B- | | -E- | | -F- | Accumulator
----------- | ---- X ---- | X index
register
----------- | ---- Y ---- | Y index register
----------- |
---- U ---- | User stack pointer
----------- | ---- S ---- | System stack
pointer
----------- | --- PC ---- | Program counter
----------- |
---- V ---- | V (alue) register
----------- | --- DP ---- | Direct page
register
----------------- | CC- | Condition code register
-----------------
| MD- | Mode / Status Register
__________________________________________________
*********
action mode
63C09 has two operation modes. One is an
emulated mode that is compatible with the 6809, and the other is a native mode
that brings out the original functions of his 63C09.
Speaking of
which, some people may think that "extended registers and extended
instructions can be used in native mode, and cannot be used in emulated mode",
but that is a mistake. The 63C09 accepts extended registers and extended
instructions in either mode.
The difference between emulated mode
and native mode is the handling of the stack at the time of interaction. When
an interrupt is applied, the contents of the register are saved on the stack.
At that time, the emulated mode saves only the conventional register, and the
native mode saves the W register of the extended register as well.
Immediately
after resetting 63C09, it is set to emulate mode. In this mode he has to be
careful when using extended registers for multitasking instead of the 6809
software working fine. For example, consider the case of using the block
transfer instruction TFM that uses the W register of the extension register as
a counter. Let's say that in task A he interrupts while using the TFM
instruction and moves to task B. If the W register is used in task B at that
time, the contents of the W register will be changed when returning to the
original task A, which will cause a malfunction (of course, when using it in a
single task or multi). Even for tasks, there is no problem when the expansion
register is used for only one task). Therefore, in emulated mode, you must
disable interrupts each time you use an extended register, save this register
on the stack, and then switch to another task.
This makes it
difficult to use expansion registers from high-speed games and OS-9, and also
causes difficult-to-use expansion instructions. Therefore, there is a native
mode, which is a mode that assumes the use of extended registers and extended
instructions. Interrupts in this mode save registers on the stack in the order
of PC, U, Y, X, DP, W, D, CC and enter interrupt processing. Note that W is
between DP and D. This means that D and W are pushed onto the stack as his
32-bit register pair Q.
Another feature of the native mode is the
shortening of the instruction machine cycle. As a result, it runs 20-35%
faster depending on the addressing mode.
The effect is particularly
noticeable in direct, extend, and inherant [kencho = remarkable, striking,
conspicuous].
--------
74 Oh! FM 1988-4
--------
[Oh!
FM 1988-4: p.75]
Please note that the V register and MD register
are not saved due to their nature even in native mode.
To switch
from the emulated mode to the native mode, write 1 to bit 0 (LSB) of the newly
installed MD gista.
By the way, in addition to the above two modes,
the 63C09 mode has a FIRQ stack evacuation mode. As you know, in 6809 fetching
FIRQ saves only PC and CC to the stack and branches to the interrupt
processing routine. However, in the case of a board microcomputer for control,
there are cases where it is more convenient to have another IRQ than FIRQ.
However, the 63C09 is pin compatible with the 6809, so you can't change the
placement of your feet. So, so that FIRQ can be used as his IRQ, the mode can
be switched softly so that all registers save the stack. Using FIRQ as an IRQ
is achieved by writing 1 to bit 1 of the MD register.
********
trap
63C09
will be trapped when the following phenomena occur.
1 When an
undefined instruction is fetched
When he divides by 0 with a DIV
instruction in a two-division instruction
When trapped, S in the
order of PC, U, Y, X, DP, B, A, CC in emulated mode, and in the order of PC,
U, Y, X, DP, W, B, A, CC in native mode. After pushing the register to the
register, it branches to the vector written at the address of $ FFF0 ($ FFF0
is RESERVE in 6809). This trap has the next interrupt priority for reset. As
an instruction to determine whether it is an undefined instruction or a zero
divide.
There is a BITMD instruction.
Because of this
trap, the software of 6809 that uses undefined instructions will not work, but
instead you will be able to build the trap library used in OS-9 / 68000 etc.
For example, assigning a floating-point processor call to an undefined
instruction allows the instruction to be hooked into an undefined instruction
trap and skipped to a processing routine. This trap library can be useful
because it can significantly reduce the size of objects.
********
Extension
instruction
The 63C09 extension instruction can be divided into an
additional instruction that increases the corresponding register of the
existing instruction and a newly established instruction.
Newly
installed instructions include inter-register operation instructions, block
transfer instructions, multiplication / division instructions, bit operation
instructions, bit operation / transfer instructions, and so on.
Additional
instructions
~~~~~~~~
In 63C09, the existing instructions have
been expanded and the corresponding registers have increased.
For
example, TSTD, ADCD, etc., which were unlikely until now, have been added.
These can be expressed using macros on the assembler in the past, but by using
them, the machine cycle can be shortened.
Also, for instructions
such as ADD and SUB, the number of corresponding instructions is increasing
due to the increase in E / F / W registers. It's like having another set of A
/ B / D registers, giving you more programming flexibility. However, note that
not all instructions that can be used in the A / B / D registers are supported
(Fig. 2).
Among the existing instructions, the TFR and EXG
instructions are probably the ones with the highest degree of addition. In the
TFR and EXG instructions, the postbyte bit pattern is used to specify the
target register. Since the number of registers is increasing in 63C09, the
combination of bit patterns is also increasing (0110-> W, 0111-> V,
1110-> E, 1111-> F), and it is in a good state even if it is register
addressing. I am. This register addressing is also used in the
register-to-register operations of new instructions. One thing to keep in mind
here is that 63C09 and 6809 behave differently if you specify a true undefined
register number.
Figure 2 Processing that can be performed with the accumulator
____________________________________
A | B | E | F | D | W | Q |
CLR | o | o | o | o | o | o | |
INC | o
| o | o | o | o | o | |
DEC | o | o | o | o | o | o | |
TST | o | o
| o | o | o | o | |
COM | o | o | o | o | o | o | |
NEG | o | o | |
| o | | |
SEX | o * | o * | | | o * | o * | |
ASL / LSL | o | o | |
| o | | |
ASR | o | o | | | o | | |
LSR | o | o | | | o | o | |
ROL
| o | o | | | o | o | |
LD | o | o | o | o | o | o | o |
ST | o | o
| o | o | o | o | o |
ADD | o | o | o | o | o | o | |
SUB | o | o |
o | o | o | o | |
CMP | o | o | o | o | o | o | |
ADC | o | o | | |
o | | |
SBC | o | o | | | o | | |
AND | o | o | | | o | | |
OR
| o | o | | | o | | |
EOR | o | o | | | o | | |
BIT | o | o | | | o
| | |
MUL | o * | o * | | | o | | |
DIV | | | | | | | o |
____________________________________
* Used as work
Inter-register operation instruction
~~~~~~~~~~~~~~~~~~
Most
of the operations on the 6809 were done with register-to-memory or immediate
values. Therefore, if we wanted to AND the values of the A and B registers,
we had to store either register in memory before performing the operation (AND
in this case). This has been resolved in 63C09, which allows
register-to-register operations. They use the same register addressing as TFR
and EXG.
The inter-register operation instructions are as
follows.
ADDR, ADCR, SUBR, SBCR,
ANDR, ORR, EORR, CMPR
Block
transfer instruction
~~~~~~~~~~~~~~~~
When moving the data in
the memory with 6809, once the data was loaded into the register, it was saved
repeatedly. This is fine, but the problem is the time it takes to process it.
Therefore, the 63C09 also has a block transfer instruction that is also found
on the Z80 and 8086.
--------
Oh! FM 1988-4 75
--------
[Oh!
FM 1988-4: p.76]
In the block transfer instruction, 1 to 2 of the
16-bit registers D / X / Y / U / S registers are used to specify the transfer
source address (source) and transfer destination address (destination).
Postbytes are used to specify registers, which take the form of register
addressing. You can also specify the source and destination in the same
register. Use the W register to count the number of bytes to transfer.
There
are four types of transfer methods. In addition to normal block transfer in
the forward direction (TFM r0 +, r1 +) / reverse direction (TFM r0-, r1-),
data is flowed one after another to addresses such as I / O ports (TFM r0 +,
r1-). There are TFM ro +, r1) and those that fill the specified block with the
specified value (TFM r0, r1 +).
Multiply / divide
instruction
~~~~~~~~~~~~~~
The 6809 had an 8-bit 8-bit
multiplication instruction called MUL, but this was just a multiplication of
the values of the A register and the B register. The 16x16-bit
multiplication instruction (MULD) provided by the 63C09 allows you to use
various addressing modes, which is more like a new installation than an
addition.
In addition, the 63C09 is equipped with 16/8 bit division
(DIVD) and 32/16 bit division (DIVQ), which also allow various addressing
modes to be used.
Bit manipulation instruction (6301 compatible
instruction)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hitachi's
HD6301 has a bit manipulation instruction as an extension instruction for
6801.
Although it was new, his 63C09 in the same 63 series has the same
instructions. These instructions logically operate the immediate data and the
contents of the memory, return the result to the memory, and change the
related condition code, which is useful when manipulating bit patterns.
Logical
operations that can be performed include logical product (AIM), logical sum
(OIM), exclusive logical sum (EIM), and logical product condition code (TIM).
The composition of the object is
<Instruction code>, <Bit
position>, <Operand>
It is in the order of.
Using
these instructions, the 6301 instruction can be executed on 63C09 using the
macro assembler. In other words, it may be possible to run embedded programs
such as OASYS Lite on FM, which is also a delicious instruction (although you
have to disassemble the ROM with guts before that).
Bit operation /
transfer instruction
~~~~~~~~~~~~~~~~~~~~
63C09 probably has I
/ O-aware bit operation / transfer instructions. These instructions have the
drawback that they only support direct mode for addressing mode, but once you
get used to it, you'll find it useful. Most of the behavior is to logically
operate the bit n of the LABEL of the direct page and the bit m of the REG
register and put them in the REG register. The bit operation / transfer
instructions are as follows.
BAND, BOR, BEOR, BIAND,
BIOR,
BIEOR, LDBT, STBT
The composition of the object is
<Instruction
code ($ 11, $ xx)>, <Post byte>, <Operand>
And, it
takes a fairly irregular configuration. Operand is direct addressing only.
Postbytes also take a special form.
Other orders
~~~~~~~~~~~~
As
other commands, there is a mode switching command first. However, the
transition from emulated mode to native mode is done by writing 1 to bit 0
(LSB) of the MD register, so use the usual LD instructions for the MD
register.
The next time a trap is applied, there is an instruction
BITMD to check whether it was caused by an undefined instruction or a division
error. It looks at the status bits (bits 7 or 6) of the MD register and tells
you where the trap occurred. However, executing this instruction clears the
status bits (bits 7 and 6) of the MD register, so you can only check once for
undefined code traps or Divide by Zero traps.
And there is
something about the stack. The 63C09 has more registers, but the current PSHS
/ PSHU does not allow them to be saved on the stack. This is because the PSHS
/ PSHU and PULS / PULU post bytes are all already allocated and there is no
room for additional. Therefore, in 63C09, the stack operation to the added
register is a separate instruction.
PSHSW, PULSW, PSHUW, PULUW
Is
used. However, this is only for the W register. Therefore, these are only
Inheren and Addressing without postbytes.
********
in
conclusion
I have explained the outline of the functions hidden in
63C09. Most of the features that I wanted to add to the 6809 with + α are
included, which is good news for the 6809 group. However, unfortunately, the
appearance time was late, so the place of activity was limited to the
modification of personal computers or industrial one-board microcomputers. As
for gaming PCs, with the current situation where he is starting to use 16-bit
CPUs such as the 68000 series, the 8086 series, and the 65816, it is unlikely
that manufacturers will ship PCs loaded with the 63C09. It is a pity that it
can only be used for remodeling FM-11 etc. that does not depend on the market
application for the time being.
In compiling this article, in
addition to the materials I analyzed, I referred to the materials analyzed by
the members of the 63C09 Analysis Committee (especially his Gigo and his
Miyazaki). 63C09 We would like to thank the people involved in the analysis
committee for their cooperation.
--------------------------------
<References>
・
63C09 Analysis Committee, "New Year's gift 63C09 had a hidden function",
NANNO-NET, January 1, 1988-
-Motorola, "MC6809-MC-6809E Microprocessor
Programming Manual", CQ Publishing, 1982
・ "6809 Instruction Pocket
Book", Oh! FM 1983 No. 4, Japan Softbank
・ Ryuta Mizutani, "Undefined
Order of 6809", I / O May 1985, Engineering Co., Ltd.
・ Susumu Hara,
"Clock of FM-11 to his 3MHz", PC World January 1987 issue, PC World Japan
--------
76
Oh! FM 1988-4
--------
[Oh! FM 1988-4: p.77]
Fig. 3 Instructions increased in 63C09 (gray part [=> * box *])
((
The
horizontal columns are from top to bottom with no prebytes, with prebytes $
10, and with freebytes $ 11. again,
The number on the lower left side of
each item is the number of cycles, and the value in parentheses is the value
in native mode. The right side is the command length.
))
[There
is a typographical error due to the editing of the manuscript. Original
contains typographical errors.]
=================================================
=================================================
================================================= =========== |
DIRECT | | | REL | ACC A / D / E | ACC B / W / F | INDEXD | EXTEND | IMMED |
DIRECT | INDEXD | EXTEND | IMMED | DIRECT | INDEXD | EXTEND |
0000xxxx | 0001xxxx | 0010xxxx | 0011xxxx | 0100xxxx | 0101xxxx | 0110xxxx |
0111xxxx | 1000xxxx | 1001xxxx | 1010xxxx | 1011xxxx | 1100xxxx | 1101xxxx |
1110xxxx | 1111xxxx |
0x | 1x
| 2x | 3x | 4x | 5x | 6x | 7x | 8x | 9x | Ax | Bx | Cx | Dx | Ex | Fx |
=================================================
=================================================
================================================= =========== |
0000
0 | NEG | (PRE) | BRA | LEAX | NEGA | NEGB | NEG | NEG | SUBA | SUBA | SUBA |
SUBA |
(None) | 6 (5), 2 | (BYTE1) | 3,2 | 4+, 2+ | 2 (1), 1 | 2
(1), 1 | 6+, 2+ | 7 (6), 3 | 2,2 | 4 (3), 2 | 4+, 2+ | 5 (4), 3 | 2,2 | 4 (3),
2 | 4+, 2+ | 5 (4), 3 |
-------- | -------- | -------- | -------- |
------------ |- -------- | --------- | --------- | -------- | -------- | ---
----- | --------- | -------- | -------- | -------- | ------- -| -------- |
| | | | * addr * | * negd * | | | | * subw * | * subw * | * subw * | * subw *
| | | | |
($ 10) | | | | 4,3 | 3 (2), 2) | | | | 5 (4), 4 | 7 (5),
3) | 7+ (6+), 3+ | 8 (6) ), 4 | | | | |
-------- | -------- | -------- |
-------- | ------------ |- -------- | --------- | --------- | -------- |
-------- | --- ----- | --------- | -------- | -------- | -------- | ------- -|
-------- |
| | | | * band * |
| | | | * sube * | * sube * | * sube * | * sube * | * subf * | * subf * | *
subf * | * subf * |
($ 11) | | | | 7 (6), 4 | | | | | 3,3 | (4), 3
| 5 +, 3+ | 6 (5), 4 | 3,3 | 5 (4), 3 | 5+, 3+ | 6 (5), 4 |
=================================================
=================================================
================================================= =========== |
0001
1 | * oim * | (PRE) | BRN | LEAY | | | * oim * | * oim * | CMPA | CMPA | CMPA
| CMPA | CMPB | CMPB | CMPB | CMPB |
(None) | 6,3 | (BYTE2) | 3,2 |
4+, 2+ | | | 7+, 3+ | 7,4 | 2,2 | 4 (3), 2 | 4+, 2+ 5 (4), 3 | 2,2 | 4 (3), 2
| 4+, 2+ | 5 (4), 3 |
-------- | -------- | -------- | -------- |
------------ |- -------- | --------- | --------- | -------- | -------- | ---
----- | --------- | -------- | -------- | -------- | ------- -| -------- |
| | | LBRN | * adcr * | | | | | * cmpw * | * cmpw * | * cmpw * | * cmpw * | |
| | |
($ 10) | | | 5,4 | 4,3 | | | | | 5 (4), 4 | 7 (5), 3) | 7+
(6+), 3+ | 8 (6), 4 | | | | |
-------- | -------- | -------- | -------- |
------------ |- -------- | --------- | --------- | -------- | -------- | ---
----- | --------- | -------- | -------- | -------- | ------- -| -------- |
| | | | * biand * | | | | | * cmpe * | * cmpe * | * cmpe * | * cmpe * | * cmpf
* | * cmpf * | * cmpf * | * cmpf * |
($ 11) | | | | 7 (6), 4 | | |
| | 3,3 | 5 (4), 3 | 5 +, 3+ | 6 (5), 4 | 3,3 | 5 (4) , 3 | 5+, 3+ | 6 (5), 4
|
=================================================
=================================================
================================================= =========== |
0010
2 | * aim * | NOP | BHI | LEAS | | | * aim * | * aim * | SBCA | SBCA | SBCA
| SBCA | SBCB | SBCB | SBCB | SBCB |
(None) | 6,3 | 2 (1), 1 | 3,2
| 4+, 2+ | | | 7+, 3+ | 7,4 | 2,2 | 4 (3), 2 | 4+ , 2+ | 5 (4), 3 | 2,2 | 4
(3), 2 | 4+, 2+ | 5 (4), 3 |
-------- | -------- | -------- | -------- |
------------ |- -------- | --------- | --------- | -------- | -------- | ---
----- | --------- | -------- | -------- | -------- | ------- -| -------- |
| | | LBHI | * subr * | | | | | * sbcd * | * sbcd * | * sbcd * | * sbcd * | |
| | |
($ 10) | | | 5/6 (5), 4 | 4,3 | | | | | 5 (4), 4 | 7 (5), 3)
| 7+ (6+), 3+ | 8 ( 6), 4 | | | | |
-------- | -------- | -------- |
-------- | ------------ |- -------- | --------- | --------- | -------- |
-------- | --- ----- | --------- | -------- | -------- | -------- | ------- -|
-------- |
| | | | * bor * | |
| |
related article: http://fms.komkon.org/comp/CPUs/6309.txt
ReplyDeleteAh, Hirotsugu's reportage. I should put that link in the main post, as well.
Delete