Misunderstanding Computers

Why do we insist on seeing the computer as a magic box for controlling other people?
人はどうしてコンピュータを、人を制する魔法の箱として考えたいのですか?
Why do we want so much to control others when we won't control ourselves?
どうしてそれほど、自分を制しないのに、人をコントロールしたいのですか?

Computer memory is just fancy paper, CPUs are just fancy pens with fancy erasers, and the network is just a fancy backyard fence.
コンピュータの記憶というものはただ改良した紙ですし、CPU 何て特長ある筆に特殊の消しゴムがついたものにすぎないし、ネットワークそのものは裏庭の塀が少し拡大されたものぐらいです。

(original post/元の投稿 -- defining computers site/コンピュータを定義しようのサイト)

Saturday, November 12, 2022

8080 Assembly Language Crib Sheet

The 8080 is messy. I have a fairly easy time remembering the 680X assembly languages. I don't have nearly as easy a time remembering the 8080 operators, allowed operands, flags, etc. 

So I'm putting up a crib sheet, mostly for myself:

8080 Registers (8 & 16 bit)
Temporary Registers B C
Temporary Registers D E
Index High/Low
H L
Accumulator/Status
PSW A
Stack Pointer SP
Program Counter PC

(Need to add some better short-short summary stuff here when I figure out how to organize it.)

R byte operands --
registers B,C,D,E,H,L,A
memory M pointed to by HL

Condition code flags (Program Status Word==PSW), in order --
Sign, Zero, (0), Auxilliary Carry, (0), Parity, (1), Carry

RP 16-bit operands --
subset of register pairs B:C, D:E, H:L, SP, PSW:A

index operands
M (H:L pair)
X:B (B:C pair), D (D:E pair)

ORG D
set origin (assembly address) to absolute address D

L EQU V
define invariant value of label/symbol

L SET V
set value of label/symbol
SET labels may be redefined.

END
end

DB/DW V
define a label and allocate and store byte or word value V there

DS SZ
define a label and only reserve space of size SZ

STC/CMC {C}
set/complement carry

INR/DCR R {ZSPA}
byte increment/decrement R/M

CMA {}
complement A

DAA {ZSCPA}
decimal adjust A

NOP
No OP

MOV Rdest,Rsrc {}
move byte data R/M
But MOV M,M is not valid.
Other than disallowed M, to self is effective NOP.

MVI R,I {}
move 8-bit immediate data from instruction stream to R/M

LDA/STA D {}
load/store (move) 8-bit data at direct (absolute) 16-bit address D to A
or 8-bit data in A to direct (absolute) 16-bit address D

LDAX/STAX X {}
load/store (move) A indexed by B:C or D:E

LHLD/SHLD D {}
load/store (move) 16-bit data at direct (absolute) 16-bit address D to H:L
or 16-bit data in H:L to direct (absolute) 16-bit address D

LXI RP,I {}
move 16-bit immediate data from instruction stream to RP
Destination can be B (B:C), D (D:E), H (H:L) or SP.

ADD/ADC R {CSZPA}
add without or with carry R/M to A
ADD A is effectively shift left, but note flags.

ADI/ACI I {CSZPA}
add without or with carry immediate date to A

SUB/SBB/CMP R {CSZPA}
subtract/compare without or with borrow R/M from A
SUB A clears A and sets the flags accordingly.
Sense of C flag in compare inverted if operand signs differ.

SUI/SBI/CMP I {CSZPA}
subtract/compare without or with borrow immediate data from A
Sense of C flag in compare inverted if operand signs differ.

ANA R {CZSP}
bit-and R/M into A
Carry is always cleared.

ANI I {CZSP}
bit-and immediate data from instruction stream into A
Carry is always cleared.

XRA R {CZSPA}
bit exclusive-or R/M into A
Carry is always cleared.

XRI I {CZSPA}
bit exclusive-or data from instruction stream into A
Carry is always cleared.

ORA R {CZSP}
bit-or R/M into A
Carry is always cleared.

ORI I {CZSP}
bit-or data from instruction stream into A
Carry is always cleared.

RLC/RRC R {C}
8-bit left/right rotate with carry R/M

RAL/RAR R
9-bit left/right rotate through carry R/M

PUSH/POP RP {},{all}
push/pop register pairs:
B (B:C), D (D:E), H (H:L), PSW (flags:A)
Condition codes only affected by POP PSW/A.

DAD RP {C}
16-bit add of register pair into H:L,
RP can be B:C, D:E, H:L, SP
DAD H is shift left with carry.

INX/DCX {}
increment/decrement register pair
RP can be B:C, D:E, H:L, SP

XCHG {}
16-bit exchange D:E with H:L

XTHL {}
16-bit exhange of top of stack with H:L

SPHL {}
16-bit move H:L to SP

PCHL {}
move H:L to PC
This is the 8080's indexed jump.

JMP D {}
jump uncoditionally to direct (absolute) 16-bit address

JC/JNC D {}
jump if C (carry) set/clear to direct (absolute) 16-bit address
(Carry/No Carry)

JZ/JNZ D {}
jump if Z (zero) set/clear to direct (absolute) 16-bit address
(Zero/Not Zero)
Effectively equal/not equal after a subtract or compare.

JM/JP D {}
jump if S (sign) set/clear to direct (absolute) 16-bit address
(Minus/Plus)

JPE/JPO D {}
jump if P (parity) set/clear to direct (absolute) 16-bit address
(Even/Odd)

CALL D {}
call unconditionally to direct (absolute) 16-bit address
Push address of next instruction on stack and jump.

CC/CNC D, CZ/CNZ D, CM/CP D, CPE/CPO D
Conditional calls, same conditions as conditional JMPs.

RET {}
return unconditionally to address saved on stack
Pop top of stack into PC.

RC/RNC, RZ,RNZ, RM/RP, RPE/RPO
Conditionally return to address saved on stack,
same conditions as conditional JMPs.

RST N {}
save address of next instruction on stack and jump to address N times 8
N is 0 through 7, yielding address from 0 to 56 on 8-byte boundaries.
Effects a software version of a numbered interrupt.
Use ordinary RET or conditional return to return.
Interrupt routine must explicitly save state of all registers used.

DI/EI {}
disable/enable interrupts
Clears/sets the INTE interrupt enable flip-flop.

IN/OUT P {}
load A from/store A to 8-bit port number P
P is an address in port space between 0 and 256.

Okay, I think I got the HTML right on that without losing any of the entries.

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